Memory Hierarchy

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Memory Hierarchy Virtual Memory Review

• Michael Holden

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Memory Hierarchy The pyramid
Recall Higher up, more expensive
faster. Going down larger slower.
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CPU Registers

• They are the fastest because they are right
  there.
• They are the most expensive to implement because
  its on the CPU.
• Number of registers dependant upon architecture
  of the CPU itself.
• Quick and easy to get to.

There they are!
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Cache

• CPU clock speeds have always been faster than
  DRAM. If a CPU had to wait constantly for the
  DRAM, its speed would not be worth anything.
• Therefore Cache was introduced.
• The differences between L1 and L2 cache are their
  locations and their size.

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L1 Cache primary

• The L1 cache is located closer to the CPU.
• Therefore it is faster and smaller.
• For the Pentium II, the cache was split into two,
  D-cache and I-cache. (Data and instructions)
• Allows for simultaneous action if the data bus
  allows (needs to be doubled).

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L2 cache

• The Level 2 cache can get pretty big since it is
  on the motherboard.
• It will run slower than L1 because it needs to
  travel a longer distance.
• For the Pentium II they tried to package the CPU
  with the L2 cache.
• The dedicated bus between the CPU and L2 ran at
  200MHz instead of the motherboards 100MHz system
  bus.
• So now, the L2 cache is on the CPU too.

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Current (Old) Processors
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Physical Memory -

• SRAM and DRAM
• SRAM is faster but more expensive.
• DRAM cheaper

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Virtual Memory

• Virtual memory was created long ago when main
  memory was expensive, scarce, and not so fast.
  
• Virtual memory conveniently
• expands the main memory by
• storing things on a hard disk.
• The area which is reserved for this purpose is
  managed by the OS and is called swap space.
• Programmers would have to
• segment their code and pass
• it through like a chain.

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Virtual Memory (cont)

• When RAM became cheaper you would think that
  virtual memory would go away.
• However larger programs emerged since programmers
  did not have to worry so much about memory space.
• This helps with the development of database
  systems.

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MMU Memory Management Unit

• Is between the CPU and memory (including the
  cache).
• It maps references to variables and functions
  from the compiler to physical references to frame
  numbers and offset addresses.
• The translation occurs in real-time, each
  access to memory.

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• The MMU creates an array, of which it only stores
  recent information since it cant hold a large
  amount of information.
• So if there is a reference to an item not there
  it needs to update.
• The TLB (Translation Lookaside Buffer) is a cache
  buffer which holds active entries from the page
  table.

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• These objects are typically not very fast at all
  but can hold a large amount of data.

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End

• Questions?
• Look at some of the previous slides, it can help.