Welcome to the ECE 449 Computer Design Lab

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ECE 448 Lecture 16
Bit CounterShift-and-Add Multiplier
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Required reading

• S. Brown and Z. Vranesic, Fundamentals of
  Digital Logic with VHDL Design
• Chapter 10.2.1, A Bit-Counting-Circuit
• Chapter 10.2.2, ASM Chart Implied Timing
• Information
• Chapter 10.2.3, Shift-and-Add Multiplier

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Bit Counter
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Pseudo-code for the bit counter

• B 0
• while A?0 do
• if a0 1 then
• B B 1
• end if
• Right-shift A
• end while

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ASM chart of the bit counter
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Expected behavior of the bit counter
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Datapath of the bit counter
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ASM chart for the bit counter control circuit
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VHDL code of the bit counter (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• LIBRARY work
• USE work.components.shiftrne
• ENTITY bitcount IS
• PORT(Clock, Resetn IN STD_LOGIC
• LA, s IN STD_LOGIC
• Data IN STD_LOGIC_VECTOR(7 DOWNTO 0)
• B BUFFER INTEGER RANGE 0 to 8
• Done OUT STD_LOGIC )
• END bitcount

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VHDL code of the bit counter (2)

• ARCHITECTURE Behavior OF bitcount IS
• TYPE State_type IS ( S1, S2, S3 )
• SIGNAL y State_type
• SIGNAL A STD_LOGIC_VECTOR(7 DOWNTO 0)
• SIGNAL z, EA, LB, EB, low STD_LOGIC
• BEGIN
• FSM_transitions PROCESS ( Resetn, Clock )
• BEGIN
• IF Resetn '0' THEN
• y lt S1
• ELSIF (Clock'EVENT AND Clock '1') THEN
• CASE y IS
• WHEN S1 gt
• IF s '0' THEN y lt S1 ELSE y lt S2 END
  IF
• WHEN S2 gt
• IF z '0' THEN y lt S2 ELSE y lt S3 END
  IF
• WHEN S3 gt
• IF s '1' THEN y lt S3 ELSE y lt S1 END
  IF
• END CASE

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VHDL code of the bit counter (3)

• FSM_outputs PROCESS ( y, A(0) )
• BEGIN
• EA lt '0' LB lt '0' EB lt '0' Done lt '0'
  
• CASE y IS
• WHEN S1 gt
• LB lt '1'
• WHEN S2 gt
• EA lt '1'
• IF A(0) '1' THEN
• EB
  lt '1'
• ELSE
• EB lt '0'
• END IF
• WHEN S3 gt
• Done lt '1'
• END CASE
• END PROCESS

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VHDL code of the bit counter (4)

• -- The datapath circuit is described below
• upcount PROCESS ( Resetn, Clock )
• BEGIN
• IF Resetn '0' THEN
• B lt 0
• ELSIF (Clock'EVENT AND Clock '1') THEN
• IF LB '1' THEN
• B lt 0
• ELSEIF EB '1' THEN
• B lt B 1
• END IF
• END IF
• END PROCESS

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VHDL code of the bit counter (5)

• low lt '0'
• ShiftA shiftrne GENERIC MAP ( N gt 8 )
• PORT MAP ( Data, LA, EA, low, Clock, A )
• z lt '1' WHEN A "00000000" ELSE '0'
• END Behavior

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Shift-and-Add Multiplier
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An algorithm for multiplication
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ASM chart for the multiplier
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Expected behavior of the multiplier
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Datapath for the multiplier
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ASM chart for the multiplier control circuit
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VHDL code of multiplier circuit (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE ieee.std_logic_unsigned.all
• USE work.components.all
• ENTITY multiply IS
• GENERIC ( N INTEGER 8 NN INTEGER 16 )
  
• PORT ( Clock IN STD_LOGIC
• Resetn IN STD_LOGIC
• LA, LB, s IN STD_LOGIC
• DataA IN STD_LOGIC_VECTOR(N1 DOWNTO 0)
  
• DataB IN STD_LOGIC_VECTOR(N1 DOWNTO 0)
  
• P BUFFER STD_LOGIC_VECTOR(N1 DOWNTO
  0)
• Done OUT STD_LOGIC )
• END multiply

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VHDL code of multiplier circuit (2)

• ARCHITECTURE Behavior OF multiply IS
• TYPE State_type IS ( S1, S2, S3 )
• SIGNAL y State_type
• SIGNAL Psel, z, EA, EB, EP, Zero STD_LOGIC
• SIGNAL B, N_Zeros STD_LOGIC_VECTOR(N1 DOWNTO
  0)
• SIGNAL A, Ain, DataP, Sum STD_LOGIC_VECTOR(NN
  1 DOWNTO 0)
• BEGIN
• FSM_transitions PROCESS ( Resetn, Clock )
• BEGIN
• IF Resetn '0 THEN
• y lt S1
• ELSIF (Clock'EVENT AND Clock '1') THEN
• CASE y IS
• WHEN S1 gt
• IF s '0' THEN y lt S1 ELSE y lt S2 END
  IF
• WHEN S2 gt
• IF z '0' THEN y lt S2 ELSE y lt S3 END
  IF
• WHEN S3 gt
• IF s '1' THEN y lt S3 ELSE y lt S1 END
  IF

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VHDL code of multiplier circuit (3)

• FSM_outputs PROCESS ( y, s, B(0) )
• BEGIN
• EP lt '0' EA lt '0' EB lt '0' Done lt '0'
  Psel lt '0'
• CASE y IS
• WHEN S1 gt
• EP lt '1
• WHEN S2 gt
• EA lt '1' EB lt '1' Psel lt '1
• IF B(0) '1' THEN
• EP lt '1'
• ELSE
• EP lt '0'
• END IF
• WHEN S3 gt
• Done lt '1
• END CASE
• END PROCESS

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VHDL code of multiplier circuit (4)

• - - Define the datapath circuit
• Zero lt '0'
• N_Zeros lt (OTHERS gt '0' )
• Ain lt N_Zeros DataA
• ShiftA shiftlne GENERIC MAP ( N gt NN )
• PORT MAP ( Ain, LA, EA, Zero, Clock, A )
• ShiftB shiftrne GENERIC MAP ( N gt N )
• PORT MAP ( DataB, LB, EB, Zero, Clock, B )
• z lt '1' WHEN B N_Zeros ELSE '0'
• Sum lt A P
• - - Define the 2n 2-to-1 multiplexers for
  DataP
• GenMUX FOR i IN 0 TO NN1 GENERATE
• Muxi mux2to1 PORT MAP ( Zero, Sum(i), Psel,
  DataP(i) )
• END GENERATE
• RegP regne GENERIC MAP ( N gt NN )
• PORT MAP ( DataP, Resetn, EP, Clock, P )
• END Behavior