Review and Problems Chapters 5, B and C

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Review and ProblemsChapters 5, B and C
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Summary

• To build a processor
• Determine which functional units are needed
• Create a basic data path
• Add multiplexors to control inputs to functional
  units
• Note control signals for functional units
• If multi-cycle, create state machine
• Implement directly, or use microprogramming

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Functional Units (no State)

• Examples weve seen
• ALU
• Multiplexor
• Adder
• (2-bit shifter)
• (Sign-extender)

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Functional Units with State

• Register
• Register file
• Memory

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Exercise 5.3

• Do we need combinational or sequential logic for
• Comparator
• Incrementer/decrementer
• Multiplier with shifters adders
• Register

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Implementing Combinational Units

• Determine the truth table
• From the truth table
• Extract Boolean equation (use Karnaugh map for
  simplification)
• Implement directly in hardware (free-form or PLA)
• OR
• Store truth table in a ROM and use inputs to look
  up
• OR
• Build from existing combinational units

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Example 2-bit Shift Register

• Input
• 2 data bits A1, A0
• 1 direction bit (0left, 1right)
• 1 arithmetic bit (0logical, 1sign-extend)
• Output
• 2 data bits S1, S0
• 1 left bit (what falls off the left)
• 1 right bit (what falls off the right)

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Example continued

• Build the shift register directly using a truth
  table
• Build the shift register using multiplexors as
  building blocks
• Show how multiple shift registers could be
  combined to shift wider numbers

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Implementing Sequential Units

• Determine states and state machine
• Each combination of outputs is a different state
• Even if two states have the same output, if they
  would lead to different states with the same
  inputs, they are different
• Create next-state logic
• Inputs state gt next state
• Create output logic
• State gt outputs
• Note this is a Moore machine

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Example Serial to Parallel

• This unit collects 2 consecutive input bits and
  puts them out on a 2-bit output bus
• Inputs
• Data (one bit), Ready (one bit)
• Outputs
• Bit1, Bit0 (2 bits output)
• DataValid (1 bit)
• If Ready is 1, then reads 2 bits in 2 clock
  cycles DataValid is set when the output is valid

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Serial-to-Parallel Implementations

• State machine
• Using 2 1-bit registers
• Using a shift register

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One-cycle processor

• Figure out all computations that need to be done
• Ensure there is a separate functional unit for
  every computation
• Example
• Adder for branch address
• Adder for pc4
• ALU for ALU op

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Example Exercise 5.19

• Suppose we wanted to add addi to the single-cycle
  machine?
• Do we need additional hardware?
• How are the datapath and control signals modified?

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Example Exercise 5.26

• Suppose that we simplified the architecture so
  that there is no offset for memory access?
• Instead of lw rd, offset(rs) wed have lw rd,rs
  (where rs contained the address)
• How is the 1 cycle architecture simplified?

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Datapath to Modify
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Simple Math Machine 1

• This machine takes 4 4-bit inputs (A, B, C, D)
  and has 1 4-bit output ((AB)-(CD))
• If the machine has 1 cycle, how many 4-bit ALUs
  are needed?
• What is the datapath, and control?

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Multicycle Processor

• Save functional units by reusing them
• Break all cycles with registers
• Whenever the output of a functional unit would
  lead back to the input of the same functional
  unit (possibly through other logic)
• More registers means more cycles in the machine

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Multicycle Processor

• Determine all possible sequences of actions
• For an instruction set architecture, this is one
  per instruction
• Simpler units might have simpler sequences
• Build a state machine to sequence
• Moore machine (one state per possible action per
  cycle)
• Inputs are control signals and data values
• Outputs are control signals

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Simple Math Machine 2

• This machine takes 4 4-bit inputs (A, B, C, D)
  and has 1 4-bit output ((AB)-(CD))
• Build a machine that can do this in multiple
  cycles with only 1 ALU
• Build a machine that can do this with as many
  ALUs as necessary but only 1 4-bit input (Inputs
  are read serially)

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Microprogramming

• Alternative way of looking at a state machine for
  control (good for large designs)
• Each control word is equivalent to a state
• Word is made up of fields, each containing an
  independent set of control signals
• Explicit sequencing field
• Assembly maps symbolic field values to sets of
  control signals

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Simple Math Machine 3

• Write a microprogram for each version of the
  simple math machine

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Exercises Combinational and Sequential Logic

• B.6 (NAND is universal)
• B.17 (Truth table for MUX)
• B.35 (D latch vs. D flip flop)
• B.37 and B.38 (Fake security device)
• B.40 (Gray Code)

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Exercises Datapath Control

• 5.8 (Add jr to single-cycle)
• 5.10 (add lui to single-cycle)
• 5.15 (effect of faults)
• 5.21 (add bne to single-cycle)
• 5.40 (add lui to multi-cycle)

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Exercises Control Implementation

• C.9 If you added each of the following
  instructions, what changes (if any) would need to
  be made to the microcode for the multicycle
  machine?
• Lui
• Jr
• Sll
• Addi