Mnemosyne: Neural Network for Pattern Recognition

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Mnemosyne Neural Network for Pattern Recognition

• ELEC 522
• Steve So, Luke Hoban

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Block Diagram
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General Algorithm
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Control Flow
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Neuron Schematic
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VHDL Hierarchy
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Floor plan
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FPGA Editor
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Floorplan for Full Custom
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System Timing

• Post Place Route Static Timing Report
• Design statistics
• Minimum period 9.964ns (Maximum frequency
  100.361MHz)
• Maximum combinational path delay 12.236ns
• Maximum net delay 4.832ns
• (Based on Maximum delay an 80Mhz clock is
  possible)

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System Timing for Full Custom

• Longest path 20ns
• Estimated frequency 50MHz
• 108 cycles per training
• 460,000 trainings per second

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XPower estimates

• Tried to generate .vcd with ModelSim
• Produced very little data for a 300 cycle sim
• Did not provide frequency estimates for signals
  in Xpower
• Quiescent power estimated at 150mW

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Progress

• Entire system coded in VHDL
• Test benches for controller, and whole system
• Controller seems to be behaving correctly
• Datapath has bugs

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Conclusion