VHDL: Labs 6

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VHDL Labs 6 7 Overview

• Jason Matalka
• matalka_at_mail.utexas.edu

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Lab 6

• Processor
• 8-bit
• 16-bit fixed-length instructions
• Only 16 instructions to implement
• 8 Registers

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Lab 6 Instructions
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Lab 6 Registers
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Lab 6 Op Codes
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Lab 6 Instruction Types
R-Type R1 f(R2,R3) (add, sub, and, or)
Rm-Type R1 f(R2) (shift, rotate)
I-Type (andi, andi, load, store, branch)
J-Type (jump to constant address)
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Lab 6 uP Block Diagram
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Lab 6 Design

• PC
• Registers
• Separate Data Instruction Memories
• Clock
• Decode/Execute Logic

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Lab 6 Memory Design

• Must have separate memories
• Instructions are hard coded
• Distributed Memory
• Essentially a look-up table
• Uses logic to implement memory
• Block Memory
• Uses on-chip memory
• No logic used
• Look at examples (on website)

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Lab 6 Strategy

• Assign values to all control signals on RESET
• You can use structural, behavioral, or mixed code
• Top-down design is a good method

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Lab 6 Questions?
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Lab 7 Overview

• Part 1 Keyboard Controller
• Part 2 VGA Controller
• Part 3 Integration

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Lab 7 PS/2 Port

• Only 2 INPUT pins
• keyboard kclk (m16)
• keyboard data kdata (m15)

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Lab 7 PS/2 Port

• Example User presses the letter a
• Users depresses the a key
• Keyboard sends make code 1C serially
• User releases the a key
• Keyboard sends the key up code F0 serially
• Keyboard sends the break code 1C serially

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Lab 7 PS/2 Port
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Lab 7 PS/2 Port

• Design
• Use 2 flip-flops to ensure clean signals
• Use shift registers to capture serial data
• Remember, 11-bits are used.

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Lab 7 VGA
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Lab 7 VGA

• 640x480 Resolution (800x512 Full)
• Dot Clock 25.175MHz
• Horizontal Freq 25.175 MHz / 800 31.5 KHz
• Vertical Freq 31.5 KHz / 525 60Hz

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Lab 7 VGA
V Sync
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Lab 7 VGA
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Lab 7 VGA

• Use 2 counters to store the values of hcount and
  vcount
• Create a 25mhz clock
• On the rising edge of clk25mhz, increment the
  hcount. For vcount, we increment only when hcount
  has reached the end of the row.
• Create a hsync signal by looking at the value of
  hcount and figure 1 as above. VSync is created in
  a similar fashion by looking at figure 2 as above.

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Lab 7 VGA

• Create a signal to determine whether the pixel is
  in the visible region as in figure 0 as above.
• If we are currently in the visible region, output
  the pixel values R,G,B, otherwise output
  0,0,0
• Finally, put all of the outputs
  R,G,B,hsync,vsync thru a set of flipflops to
  ensure no combinational logic delays will
  interfere with the output display

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Lab 7 Integration
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Lab 7 Integration
Block Diagram Example
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Lab 7 Questions?