ECE 449: Computer Design Lab

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ECE 449 Computer Design Lab
TAs
Tuesday session Pawel Chodowiec Thursday
session Nghi Nguyen
Coordinator Kris Gaj
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Tasks of the course
Advanced course on digital system design with VHDL
Introduction to FPGA technology
Testing equipment

• writing VHDL code
• for synthesis
• RTL VHDL
• state machines
• test benches

• hardware
• Xilinx FPGAs
• software
• Aldec simulator
• Xilinx ISE

- oscilloscope - logic analyzer
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Subset of VHDL used in ECE 449
VHDL model
structural
behavioral
Not required
data flow
algorithmic
Concurrent statements
Sequential statements
Required

• Registers
• State machines
• Test benches

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Structural VHDL
Major instructions

• component instantiation (port map)
• component instantiation with generic
• 
  (generic map, port map)
• generate scheme for component instantiations
• 
  (for-generate)

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Data-flow VHDL
Major instructions
Concurrent statements

• concurrent signal assignment (?)
• conditional concurrent signal assignment
• 
  (when-else)
• selected concurrent signal assignment
• 
  (with-select-when)
• generate scheme for equations
• 
  (for-generate)

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Algorithmic VHDL (subset)
Major instructions
Sequential statements
General

• process statement (process)
• sequential signal assignment (?)

Registers

• if-then-else statement

State machines

• case-when statement

Testbenches

• loops (for-loop, while-loop)

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Digital system design technologies
ASICs
FPGAs
Microprocessors
Computer Organization
ECE 445 ECE 442 ECE 447
ECE 431
ECE 449
Digital Computer Design Interfacing
Digital Circuit Design
Computer Design Lab
Single Chip Microcomputers
Digital Integrated Circuits
ECE 586 ECE 680 ECE 681 ECE 645
Microprocessors
ECE 511 ECE 611
Advanced Microprocessors
VLSI Design Automation
Physical VLSI Design
ECE 681 ECE 645
Computer Arithmetic
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FPGAs vs. ASICs
FPGAs
ASICs
Off-the-shelf
High performance
Low development costs
Low power
Short time to the market
Low cost (but only in high volumes)
Reconfigurability