Quantum Random Number Generator

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Quantum Random Number Generator

• Project 40
• Jason Agne and Jwo-Shiun Yang

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Introduction to the Project

• Practical Applications
• Encryption/Security
• Simulations
• Video Games

• History
• Current source of random numbers is the
  computer clock not perfect
• Quantum random number generation relies on
  inherent uncertainties of Quantum Mechanics it
  must be random
• The trick is to exploit that and turn it into a
  digital signal.

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Introduction to the ProjectThe old approach
Detector
11001
Laser
Beam Splitter
Current Commercial QNG 10 Mbits/s
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Introduction The old approachLimitations
Single photon production is not easy especially
at an exact rate (impossible)
But to properly be a digital output, it must be
exact and constant
Timing ranges were used to rectify this timing
issue
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Introduction The old approachLimitations
On a single-photon level, there can only be a
probability of emission
P
1
This requires an output to wait for a
determined time to ensure the system had an
adequate chance to emit a photon
t
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Introduction Our approach(proposed by Prof.
Kwiat)
Rather than worry about the uncertainty of the
timing, we exploit it!
P
1

1. Laser is turned on
2. Time until first emission is recorded
3. Time until second emission is recorded

t1
t2
t
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Introduction Our approach(proposed by Prof.
Kwiat)
Rather than worry about the uncertainty of the
timing, we exploit it!
is
a random number!
t1
t2
-
Not only that, but it can correspond to many
bits, not just one. (resolution of detection)
Suppose we have a laser emitting single Photon
per pulse at 10MHz Bit rate ( of bit per
photon) (Frequency) 17 bits 10MHz
170Mbits/s
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Three semesters of effort

• Spring of 2006 Waveform generator
• Suhail Barot
• Aditya Vadrevu
• Abhinauv Kapoor

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Three semesters of effort

• Spring of 2006 Waveform generator

• Fall of 2006 High-speed Time to Digital
  Convereter (TDC)
• Charles Ruiz
• KanKan Yu
• Mike Noone

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Three semesters of effort

• Spring of 2006 Waveform generator

• Fall of 2006 High-speed TDC

• Spring of 2007 The Hasher

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Overview of our project

• Function occurred in four steps
• Program the TDC using Xilinx FPGA board
• Underwent an Exponential Debiaser
• Filtered into an appropriate Time Bin
• Was stored in memory as a usable output

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TDC-Time to Digital Converter

• From ACAM mess electronics
• Internal Registers needs to be configured

Stop-Trigger
Start-Trigger
ACAM TDC-GPX
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TDC State Machine
min. require
tS-AD Address setup time 2 ns
tS-DW Write data setup time 5 ns
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TDC State Machine
min. require
tS-AD Address setup time 2 ns
tV-DR Read data valid time 5 ns
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Program Testing
Configuring registers 4 and 5
4
5
4
5
Chip Select
ADDR(2)
ADDR(0)
Write
Register 4 5
ADDR 0101 0110
D(27-22) 010000 000011
D(24)
?x 2.08MHz 480 ns Check with ( of reg)( of
state each)(Clk period) 212(1/50MHz) 480 ns
D(26)
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Program Testing
Dout (V) 0.007 0.017 0.007 0.014 0.1 0.091 0.102 0.019 0.006 0.379 0.368 0.362
Logic 0 0 0 0 0 0 0 0 0 1 1 1
Hex 0 0 0 0 0 0 0 0 7 7 7 7
0.376 0.360 0.373 0.357 0.359 0.352 0.011 0.016 0.440 0.091 0.009 0.091 0.013 0.105 0.110 0.350
1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1
F F F F C C C C 8 8 8 8 1 1 1 1
High Output from TDC 0.34V
Low Output from TDC
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Bins

• Bins correspond to a range of values.
• Used to recalculate a distribution
• A uniform distribution of outputs is necessary,
  as, for random numbers to be considered random,
  each possible number should be equally probable.

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Four-bin example
This is an example of a biased output
The count is the running sum of each output of
the TDC
Separating these into four bins means that
anything within the range of a bin will put out
one of only four numbers
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Four-bin example

• A regular exponential distribution is converted
  into only four possible outputs
• In this case, we see there is a clear bias
  towards bin 1.

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Rebinning

• This is remedied by altering the bin ranges.
• Those with a higher count get a shorter range,
  thus reducing the rate of counts to match the
  other bins.

Each number will then correspond to a two-bit
output, and each with a 25 probability.
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Data from the TDC

• The distribution is very likely to be
  exponential, and possibly to an extreme degree
  (depending on operating conditions)
• We designed an exponential debiaser that attempts
  to re-bin an extreme exponential input
• This is done before the data even enters the real
  time bins

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The Exponential Debiaser

• A comparatively short module that takes a value
  set for the debiaser, and divides it into
  sub-bins based on that number
• A total of 30 unique Exponential modules were used

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The Exponential Debiaser

• Designed for inputs with an extreme exponential
  bias.
• The contents of the first sub bin are stretched
  out across all but the last.
• All but the first sub-bin is squeezed into the
  last sub bin.

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The Exponential Debiaser example

• Everything on the left side of 1 will get
  stretched out to 2
• Everything on the right side of 1 will be
  condensed into 2

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The Exponential Inhibitor

• The distribution is now far less exponentially
  biased (but not completely)
• This was an example of a four bin recalculation.
  Our Inhibitor can produce a maximum of 215

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Exponential debiaser loses data

• Increments in powers of 2
• Divides into 2n sub-bins (where n can be a max of
  15)
• Each bin will then have a range of 226-n
• For n 15, each number not in the first bin will
  be compressed into one number in the last bin,
  and being truncated in the process
• This shouldnt be used except for dealing with a
  heavy exponential bias

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The Time Bins

• 4096 Bins
• Each with a Unique ID
• ID corresponds to a bin number

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The Time Bins

• Range is also stored
• Incoming data is tested against the range along
  with information about the max of the previous
  bin
• If it is found to be in that range, the bin
  number is passed instead of the random number
• That number also becomes flagged

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The Time Bins

• From then on, it will be recognized as having
  found its bin, and corresponding random number
  (the flag disables any second recognitions
• This is a long process, but the best way we came
  up with, to stay in sync with the input

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Writing the Ranges

• We wanted to allow for full control over the bin
  widths
• The register for each range is 216 bits wide

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A small delay

• These time bins each run on one clock cycle
  (20ns)
• There are 4096 of them, which means there is a
  80 micro-second delay between the input and
  output
• The rate of output, however, is still the same

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Test for Randomness

• Not a detailed test for randomness
• The device was designed for readings from a
  device that was inherently random. If the data is
  tampered with, it will cease to be random at all
• Three registers that tallied a particular pattern
  at three four-bit ranges from the output
• Each bit of equivalent significance, of these
  registers, was compared every clock cycle.
• A total of eight bits, when more than four were
  not equal, an error was flagged.

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Challenges/Improvements

• Problems with loading the TDC
• Uses amp-driven logic, instead of Voltage (the
  FPGA does not acknowledge this)
• Output of the FPGA is not stable (loading must be
  done slowly)
• Programming size constraints
• 4096 bins, each its own module, did not fit into
  the FPGAs memory

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Recommendations

• It is recommended that the TDC be made compatible
  with TTL logic (it uses current signals).
  Additional circuit design which is need for all
  the data bus sign (28 bits)
• If one can find a more reliable alternative to an
  FPGA, it would likely be in their best interest
• with Larger built-in memory. Such as the Virtex
  series FPGAs from Xilinx

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Thank You

• Professor Kwiat (The one who came up with this)
• Evan Jeffrey (Professor Kwiats grad. student)
• Bob Schoonover (Our TA)
• Prof. Janak Patel (for keeping great ECE 385
  lecture notes)

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Questions?