Hall D Level 1 Trigger

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Hall DLevel 1 Trigger
Dave Doughty 7/23/03 Hall D Electronics Review
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Outline

• The Challenge
• The Architecture
• The Algorithm
• Real hardware the link

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Hall D - The Numbers

• According to Design Report (Table 4.7 - 9 Gev)
• Tagged Photon Rate 300 MHz
• Total Hadronic Rate 365 KHz
• Tagged Hadronic Rate 14 KHz
• Conclusions
• Trigger needs better than 25-1 rejection
• Tag event is nearly useless in trigger

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Triggering

• Factor of 25 is tough
• Requires essentially full reconstruction to
  separate on photon energy!!
• Hard to design hardware up-front to do this
• Hard to do it in 1 pass
• Hard to do it fast
• Conclusion
• Do it in 2 stages - 1 hardware 1 software

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Photon Energy Spectrum
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Cross Section
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Photon Rates
Start _at_ 107 g/s Open and unbiased trigger Design
for 108 g/s 15 KHz events to tape
Level 1 trigger system With pipeline electronics
Software-based Level 3 System
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Trigger Rates
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L1 Trigger Data What is Available?

• Track counts in
• Start Counter
• Forward TOF
• Energy in
• Barrel Calorimeter
• Forward Calorimeter

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L1 Trigger Definition What do you Want?

• Minimum/Maximum/Exact number of tracks in
• Start Counter
• Forward TOF
• Minimum or Maximum for energy in
• Barrel Calorimeter
• Forward Calorimeter
• Time window for matches
• Output delay from trigger/timestamp match

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L1 Trigger

• Four separate subsystems
• Start Counter - compute number of tracks
• Forward TOF - compute number of tracks
• Barrel Calorimeter - compute energy
• Forward Calorimeter - compute energy
• Each subsystem computes continuously - at the
  pipeline rate of the FADC pipelines - 250 MHz
• 4 level computing hierarchy
• Board -gt Crate -gt Subsystem -gt Global

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L1 Trigger
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Trigger Hierarchy - lower two levels

• Sums/counts computed on each board
• In Xilinx FPGA (reprogrammable) on each board
• Allows time window in programmable range
• Backplane routes board results to crate summers
  
• Sums/counts in each crate
• 1-2 boards/crate
• allows additional windowing
• High speed link routes crate results to subsystem
  processor
• More on this later

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Trigger Hierarchy STP and GTP

• Subsystem Trigger Processor (STP) computes sums
  for entire subsystem
• Timestamped - 12 bits at 250 MHz allows 16 ms
  rollover (Synced to master clock)
• High speed serial link routes subsystem event
  report (SER) to Global Trigger Processor (GTP)
• GTP Receives and buffers SERs from each subsystem
• Has multiple internal processors, each looking
  for one of eight (16) triggers
• Output to electronics is Programmable Delay
  after computed trigger event time

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Timing

• Flight/Detector Time 32 ns
• PMT latency 32 ns
• Cables to FEE 32 ns
• FEE to trigger out 64 ns
• Crate sum 64 ns
• Link to subsystem 128 ns
• Subsystem trigger processing 256 ns
• Transfer SER to GTP (64 bits) 256 ns
• GTP 512 ns
• Level 1 output to FEE 128 ns
• TOTAL 1.504 mS - design FEE for 3 ms (768
  stage)!

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Trigger Simulation

• Genr8 create events
• HDGeant simulate events
• hddm-xml convert output to XML
• JAXB create Java objects for XML description
• JAS for analysis
• Function Optimization for GLUEX

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(No Transcript)
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Particle Kinematics
g p ? X p ? KK-pp- p
Most forward particle
All particles
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Reactions

• 12 datasets (120,000 events)
• 4 Reactions simulated at 9 GeV
• X(1600) n -gt ?0 ? n-gt n ? ?- ?
• X(1600) n -gt Eta0 ? n -gt ? ? ? n
• ? p -gt ? ?- p
• X(1600) ?0 -gt ? ?- ? n ?0 -gt ? ?- ? n ?
  ?
• 3 of 4 are simulated at 1 and 2 GeV
• 2 Background Delta Reactions
• ? -gt n ?
• ? -gt p ?0

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Event Characteristics

• High Energy (9 GeV) Events
• More energy
• Greater fraction of energy in the forward
  direction
• Greater track counts in forward detectors
• Background Events
• Less energy overall
• More energy radially
• Track counts larger in side detectors

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Scoring

• Score the results of the GA
• Background number cut / total events
• Good 2( 1 - (number cut / total events) )
• Give the good event data as much weight as the
  background
• Divide by 16 (8 Bkgrd 2(4 Good))
• Result lt 1.0

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Conditional Trigger

• Use conditional statements to trigger.
• Fairly successful formula
• If Energy in Forward Cal lt .5 GeV and Tracks in
  Forward TOF 0
• Or
• If Total Energy lt .5 GeV and Forward Cal Energy
  lt Barrel Cal Energy
• Cut

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Conditional Trigger Results

• Eval Score 0.786

REACTION TOTAL CUT NOT CUT CUT n3pi_2gev 10
000 3088 6912 30.88 n3pi_1gev 10000 4507 5493
45.07 pro2pi_2gev 10000 4718 5282 47.18 pro2
pi_1gev 10000 6106 3894 61.06 e2gamma_1gev 1000
0 4229 5771 42.29 e2gamma_2gev 10000 5389 4611
53.89 delta_npi 10000 8199 1801 81.99 delt
a_ppi0 10000 9773 227 97.73 n3pi_9gev 9851 2
5 9826 0.25 e2gamma_9gev 9962 4 9958
0.04 pro2pi_9gev 9942 30 9912
0.30 xdelta_9gev 10000 50 9950 0.50
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Functional Trigger

• Variables
• TTOF - Tracks Forward TOF
• EFCal - Energy Forward Calorimeter
• EBCal - Energy Barrel Calorimeter
• Coefficients
• EFM - Energy Forward Cal Multiplier
• TFM - Tracks Forward TOF Multiplier
• RM - Ratio Multiplier
• Z - Offset

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Functional Form

• Zgt TFMTTOF EFMEForCal RM((EFCal
  1)/(EBCal 1))
• How do we decide what values to assign the
  coefficients and Z?
• Use a Genetic Algorithm (GA).
• Scoring the GA
• if Bkgrd Event and is Cut 1
• if Good Event and isn't Cut 5
• if Good Event and is Cut 50
• if Total number Good Events Cut gt 50 reset

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Results - Unchanged Energy
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Energy Deposition

• What if the hadronic energy deposition is wrong?
• Modified original data
• 20
• -20
• Reapplied GA
• Results same!

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Results

• The methodology works for simulations.
• Good Events
• Cuts less than 0.5
• Background Events
• Average Cut 72
• Range 41 to 99.99
• Varying hadronic energy deposition doesn't change
  results

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Gluex Energy Trigger Moving Data

• 250 MHz 8 bit flash ADC
• 16 (?!) Flash ADC channels/board
• 16 boards/crate -gt 256 channels/crate
• 576 channels in barrel calorimeter -gt 3 crates
• 2200 channels in forward cal -gt 9 crates
• Energy addition in real time
• 256 8 bit channels/crate -gt 16 bit sum
• If 256 12 bit channels/crate -gt 20 bit sum
• Each crate must pump 20 bits of data at 250 MHz
  or 625 MBytes/s
• Gluex trigger needs crate-to-crate transfer of
  600 MBytes/sec.

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Gluex Energy Trigger - III
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Desirable Features

• High speed - 625 MByte/sec
• Optical preferred
• More flexibility in trigger location
• No noise issues
• Easy-to-use interface
• Daughter card design might be good
• Minimizes layout issues of high speed signals if
  a single, well tested, daughter card design is
  used.

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S-Link

• An S-Link operates as a virtual ribbon cable,
  moving data from one point to another
• No medium specification (copper, fiber, etc.)

• 32 bits
• 40 MHz
• 160 Mbytes/s

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HOLA (High speed Optical Link for Atlas)

• Newer serializer/deserializer (serdes) chips,
  such as the TLK2501 meet or exceed 160 MBytes/s
  requirement
• HOLA is the next generation S-Link card using
  these chips
• The HOLA card has the following main features
• Uses TI TLK2501 for higher speed
  serialization/deserialization
• Data link clock is 125 MHz (_at_ 16 bits)
• Data link speed is 250 MBytes/s
• Actual throughput is limited by S-Link to 160
  MBytes/s
• Will be cheaper than older ODIN card

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HOLA at JLAB JOLA

• Obtain license from CERN
• Wait for CERN results.
• Modify design as needed.
• Fabricate our own JOLA boards.
• All S-Link cards are supported by a testing
  platform which consists of
• SLIDAD (Link Source Card)
• SLIDAS (Link Destination Card)
• SLITEST (Base Module)

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S-Link Testing

• This test interface will drive the S-Link

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Test Setup (SLITEST) - Base Module
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Setup Continued (JOLA)
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Setup Continued (Source Card)
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Setup Continued (Destination Card)
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JOLA Status

• Initial testing shows that both of the S-Link
  ends (LSC LDC), are correctly sending/receiving
  the data.
• Further testing will be aimed to
• Enhance understanding of the S-Link Protocol
• Determine the BER (bit error rate) of the link

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S-Link64

• The S-Link cannot keep up. It has a throughput
  of 160 MBytes/sec, and we need at least 500 - 650
  MBytes/sec.
• The S-Link64 is an extended version of the
  S-Link.
• Main Features
• Throughput 800MBytes/sec
• Clock Speed 100MHz
• Data size 64 bits
• Second connector handles extra 32 bits

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S-Link64 Proof of Concept

• The S-Link64 has been tested using a PCI card.
• Physical connection is LVDS on cable.
• 10 m max length.

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The next stepJOLT (Jlab Optical Link for data
Transport)

• S-Link64 will work for us (actually it is faster
  than we need), but a copper cable with a 10 m
  cable length will not.
• Xilinxs new V-II Pro offers nice features for
  next gen.
• The V-II Pro chip can replace both the Altera
  FPGA as well as the TI TLK2501.
• PowerPC 405 Processor Block
• Has 4 or more RocketIO Multi-Gigabit transceivers
• Each RocketIO has 3.125 Gbps raw rate -gt 2.5 Gbps
  data rate
• 10Gbps (1.25 Gbyte/s) if 4 channels are used.
• The full S-Link64 spec requires 3 lanes
• Error correcting will likely require 4 lanes

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JOLT 1 and JOLT -2

• JOLT will give a crate-to-crate transfer rate of
  4 x 2.5 Gbit/s or well in excess of S-Link64 spec
  of 800 Mbyte/s
• First design is Slink (Jolt-1)
• One lane version
• Easily testable with current support boards
• Second design is Slink-64 (Jolt-2)
• CERN is interested in our development.

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Conclusion

• Have an algorithm and rough design for the Level
  1 trigger
• Have simulated the algorithm for Level 1 with
  good results
• Have a roadmap to get to very high speed links
  supporting fully pipelined Gluex triggers
• Borrows liberally from existing designs. Is
  technically feasible today
• All we need is CD0!