D RunIIb Trigger Upgrade: Status and Review Response

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DØ RunIIb Trigger UpgradeStatus and Review
Response

• Darien Wood
• for the DØ Trigger Upgrade Group

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The Run IIb Trigger System
Detector
Level 1
Level 2
7 MHz
2.5 kHz
1 kHz
CAL
L1Cal
L2Cal
Cal-TRK
c/f PS
L1PS
L2PS
CFT
L1CTT
L2CTT
SMT
L2STT
L1Mu
MU-TRK
MU
L2Mu
FPD
L1FPD
Global L2
Lumi
Framework
New (or replaced) System
L3/DAQ
50 Hz
Level 3
Enhanced System
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Upgrade L1 Cal Major features

• Calorimeter trigger upgrade
• sharpens turn-on trigger thresholds
• more topological cuts
• Largest subproject in the trigger upgrade
• Will require removing the existing Cal trigger

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L1 CalTrack Major features

• Exploit new L1Cal trigger
• Improve Run IIa f matching granularity x8
• Needed in triggers for Higgs searches
• electrons in WH and H WW modes
• taus in H tt and H tn
• Fake EM rejection is improved by x2
• Fake t rejection is improved by x10
• Very modest upgrade modeled on existing Mu-Track
  match system
• Very few changes with respect to Mu-Track

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Upgrade L1CTT Major features

• Level 1 Central Track Trigger (CTT) essential for
  electrons, muons, taus (WH?l?jj)
• Tracking trigger rates sensitive to occupancy
• Upgrade stategy
• Narrow tracker roads by using individual fiber
  hits (singlets) rather than pairing adjacent
  fibers (doublets)
• Cal-track matching

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Scope of Upgrade L1CTT

• Original idea was to simply replace FPGAs to
  newer larger ones that allow more equations
• Have recently upscoped the project to allow
  monitoring and debugging capability
• The project now involves replacing two crates of
  electronics and the crates themselves
• All elements in this upgrade have been designed
  to minimize commissioning time and simplify
  debugging

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Upgrade Level 2 Major features

• Level 2 STT simply buy more boards to include
  the new layer 0
• Level 2 Processors. Just buy new faster
  processors to allow more functionality at this
  trigger level

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Management structure
WBS 1.2 Trigger Upgrade P. Padley (Rice), D.
Wood (Northeastern)
WBS 1.2.1 Level 1 Calorimeter M.Abolins(MSU),
H.Evans(Columbia)
Project is largely university based
WBS 1.2.2 Level 1 Cal-track match K. Johns
(Arizona)
WBS 1.2.3 Level 1 Tracking M. Narain (Boston),
Don Lincoln (FNAL)
WBS 1.2.4 Level 2 Beta upgrade R. Hirosky
(Virginia)
WBS 1.2.5 Level 2 STT upgrade U. Heintz (Boston)
WBS 1.2.6 Trigger Simulation M. Hildreth (ND),
E. Barberis (NEU)
WBS 1.2.7 AFE upgrade (Pending) A. Bross (FNAL)
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WBS 1.2.1 L1Cal
Clustering
ADCdigital filtering
Global sums topological
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L1 Cal progress since July 16

• ADF v.2 design complete estimate completion of
  layout in 2 weeks
• thorough attention by lead engineer (Dan Edmunds)
  to details of design and layout
• visit by Marvin Johnson to MSU in August
• review of design
• consulting on noise immunity issues
• SCLD benchtest completed on final module

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ADF v.2 Layout

• Traces
• 4279 completed
• 428 in progress
• 1052 remaining (all digital)
• Channel link section took longer than anticipated

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SCLD

• SCLD (Distributes SCL for the ADF system)
• A prototype has been used successfully in
  integration tests.
• Final (multichannel) board has successfully
  passed bench tests at Saclay

Final Multichannel SCLD
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BLS to ADF cables and staging area

• UIC and Fermilab completed design layout of
  transition elements in August
• Pleated foil cables
• Paddle transition card
• New racks set up in sidewalk area at end of August

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TAB and GAB

• Additional small board designed at Nevis to test
  GAB communication with Trigger Framework
• Orders placed for all remaining TAB and GAB
  components
• Production readiness review for TAB in Sep/Oct
• Continued progress on firmware and test software

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L1CalTrack Trigger Overview
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Cal-track progress since July 16

• Production MTCM fabricated and assembled
• MTT MTCxx/UFB MTCM MTT loop test
  established
• Serial inputs from test card
• Simple trigger algorithm on MTCxx/UFB
• Trigger output to test card via crate manager
• Compare hardware and expected result
• Resistive load built to test L1CalTrack and L1MU
  supplies (thank you Valerie Tokemenin)
• Prep work for collision hall cable termination

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Production MTCM
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Level 1 Central Track Triggerprogress since July
16 (1)

• Combined DFEA motherboard-daughterboard
• 5 PCBs fabricated
• 2 boards stuffed (recd Aug 4th)
• still missing 48V converters work around for
  now
• Passed power-up and JTAG programming tests
• DFEA stand alone tester
• Two boards received back from assembler
• Used in some preliminary tests of DFEAs
• Firmware software mostly done
• Remaining commission SLDB receiver

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DFEA pre-prod (w/ integrated motherboard)
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DFEA stand-alone tester
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Level 1 Central Track Triggerprogress since July
16 (2)

• New DFE crate backplane
• PCBs finished end of July
• connectors installed by Bustronics in August
• Received at Fermilab 11 Aug
• Alignment looks good
• Further testing once power supplies are received
  (shipped last week)
• LVDS splitters
• assembly finished end of August
• Test completed
• Installed on platform

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Level 1 Central Track Triggerprogress since July
16 (3)

• New DFE crate controllers
• Two PCBs arrived 11 August
• Stuffed by Bob Jones technicians
• No major problems found
• Firmware development
• Ethernet interface 100
• Backplane interface 95 (testing)
• SCL receiver 75 (testing)
• Communicating with Linux host PC with no problems

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L1CTT parallel chain
Mixer
DFEA crates (current)
CTOC, etc
LVDS splitters
Extra CTOC, CTTT
Fiber signals
Partial prototype DFEA crate (upgrade)
Prototype crate controller (upgrade)
Trigger framework timing (Serial command link)
link
Parallel slice of upgrade prototypes to be
installed in Aug 04 shutdown
PC
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L1CTT 04 Shutdown progress

• Completed
• Installed two LVDS splitters between mixer and
  DFEA
• System checked OK
• Will split 4 sectors
• LVDS cables checked OK
• SCL cables confirmed to be working
• Space check in PWO2 for upgrade DFEA crate
• ODH safety hardware will have to be moved
• Still to do
• Install upgrade DFEA crate on platform (PW02) (3
  days)
• Install and cable additional CTOC and CTTT (3
  days)
• Verify current system is unaffected by
  modifications (1 w)
• Installation of new DFEA prototypes and new Crate
  Controller can occur on short accesses (2 hrs)
  if necessary once above work is completed

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L2 Beta Upgradeprogress since July 16

• Work in July/August to get the Concurrent Tech
  cPCI CPU to work with the 9u motherboard
• mapped out all signals on cPCI connectors
• Surveying market for fallback CPUs in case
  compatibility issues are not resolved
  (connections on both main board mezzanine)
• Algorithm development at UVA coarse vertexing

Concurrent Technology P220
Dual P4 2GHz Hyperthreading
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STT upgrade

• This upgrade is simply making more of the boards
  that are currently used to allow for the
  inclusion of layer 0
• Production Readiness Review this Friday (10 Sept)
  in Boston, chaired by Jim Linnemann

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Simulation progress since July 16th

• L1cal
• variety of small variations of sliding window
  algorithm studies for EM triggers
• optimization point similar to current L2 EM
  algorithm
• trigger rate tool adapted to implement sliding
  windows algorithms
• uses real collider data as input
• accounts for correlations and combined rates of
  full trigger list
• L1CTT
• Run IIa simulation package being restructured
• will be much more easily adapted to Run IIb

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Recommendations from July Directors Review

• Secure the manpower for all installation needs
  in the 2004 shutdown to allow testing during the
  data taking in FY05
• Additional engineering technical help obtained
  for CTT. Shutdown progressing well.
• Establish a forum (presumably through the
  Director for Research) for ongoing dialog with
  CDF and the AD on the timing of the FY05
  shutdown
• ...

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Recommendations from July Directors Review
(cont.)

• It would be helpful to have a presentation on
  trigger simulation and validation efforts some
  time in early 2005
• Agreed. Some progress will be reported to the
  collaboration at the Sept. collaboration meeting
• Simulations for AFE II are a priority right now
• It would be useful to have a presentation of
  SC-IPC task list around the same time
• Agreed. Draft first report of SC-IPC released to
  the collaboration in late August

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Triggers Summary

• L1cal
• Main focus is ADF v.2 layout
• Progress in BLS cable transition
• L1caltrack
• MTCM production finished
• Installation work in progress in collision hall
• L1CTT
• New boards in hand being tested
• DFEA/M pre-production, DSAT, DFE controller
  prototype
• Activity progressing in shutdown for parallel
  chain
• L2
• Beta hardware tests and algorithm development
• STT PRR this week
• Simulation
• Cal algorithm optomization
• More extensive combined simulations with real
  data
• Directors review July 04
• Recommendations being followed

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Backups
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ADV v.2 layout

• straight lines indicate traces still to be routed
• mostly on FPGAs

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Preproduction MTCxx with Prototype MTFB
UFB
SLDBs