Ultimate Low Cost Analog BIST - PowerPoint PPT Presentation

1 / 26
About This Presentation
Title:

Ultimate Low Cost Analog BIST

Description:

Ultimate Low Cost Analog BIST. Marcelo Negreiros, Luigi Carro, Altamiro A. Susin ... Programa de P s-Gradua o em Computa o - PPGC. Porto Alegre, RS, Brazil ... – PowerPoint PPT presentation

Number of Views:35
Avg rating:3.0/5.0
Slides: 27
Provided by: mnegreiros
Category:
Tags: bist | analog | cost | low | luigi | ultimate

less

Transcript and Presenter's Notes

Title: Ultimate Low Cost Analog BIST


1
Ultimate Low Cost Analog BIST
Universidade Federal do Rio Grande do Sul -
UFRGS Instituto de Informática Programa de
Pós-Graduação em Computação - PPGC Porto Alegre,
RS, Brazil
  • Marcelo Negreiros, Luigi Carro, Altamiro A. Susin
  • negreiro,carro,susin_at_inf.ufrgs.br

40th Design Automation Conference - DAC2003 June
02-06, 2003, Anaheim, California, USA
2
Introduction
SoC Testing
3
SoC testing - Analog BIST
  • Desirable analog BIST features
  • low analog area overhead digital overhead is
    preferred
  • reuse system resources minimal system overhead
  • few analog measurement points
  • low performance degradation
  • low cost.

4
Analog testing (1)
  • HIGH COST

Analog circuit
5
Analog testing (2)
  • VARIABLE LOAD
  • TEST SERIALIZATION

Analog circuit
6
Analog testing (3)
1-bit ADC
  • LOWEST COST
  • PARALLELISM

1-bit ADC
1-bit DAC
1-bit ADC
Analog circuit
7
Analog BIST approach based on a low cost sampler
and signal generator
AD
Analog Core
DSP
Processor
DA
Test Core
Mem
Digital
Digital
Core B
Core A
SoC
  • multiple test points can be analyzed
  • analog switches/muxes are not required
  • the analog circuit observes a constant load.

8
Presentation topics
  • Power Spectrum Density (PSD) based analog test
  • Test example
  • Analysis
  • Conclusions

9
PSD-based analog testsystem identification
  • Transfer function identification based on noise
    (all frequency band is excited at the same time)

frequency domain
10
PSD-based analog testwhat is required?
PSD
  • Reference PSD
  • (fault-free circuit)

frequency
PSD
  • CUT PSD
  • (faulty circuit?)

frequency
11
PSD-based analog testDistance measurement
PSD
frequency
12
PSD-based analog testDistance threshold
PSD
frequency
13
PSD-based analog testDistance evaluation
Distance
dt
Distance threshold
0
CUT PSD deviation from reference PSD ()
14
Ultimate low cost bist requirements1-bit DAC
and 1-bit ADC
Analog circuit
1-bit DAC
1-bit ADC
1-bit ADC
Test core
15
Single-bit quantization of noise
  • If the input signal is a normal stationary
    process (zero mean)

The autocorrelation is transferred through the
non-linearity, by a scaling factor.
16
Signal generator output PSD
  • multi-bit and 1-bit gaussian noise
  • Matlab simulation

17
ADC input PSD comparison
  • Linear filter
  • Quality factor (Q) changes -90,-50,0,50,90

90
90
0
0
  • multi-bit data
  • one-bit data
  • power normalization

18
Distance obtained from previous PSD comparison
  • Linear filter
  • Quality factor (Q) changes -90,-50,0,50,90

90
0
90
0
  • multi-bit data
  • one-bit data

19
Test example
Continuous time state variable filter ITC97
analog and mixed-signal benchmarks
from http//www.coe.uncc.edu/cestroud/analogbc/mi
xtest.html
20
Testing a state variable filter
filter
generators HP33120A
data acquisition AD 2181 ezkit
comparators
21
Test details
  • 9 passive components R1-R7,C1,C2
  • Faults inserted
  • catastrophic open/short (18)
  • large parametric 50 (18)
  • small parametric 20 (18)
  • Evaluated test performance for
  • 1) 12800 samples
  • 2) 51200 samples
  • 3) 16-bit AD, 8-bit DA and 12800 samples

22
Test results faults not detected
1) 12800 samples
Faults
open/short
0/18
50
5/18
20
18/18
23
Analysis (1)
  • Test comparison 1-bit x multi-bit processing
  • 1-bit 23 out of 36 parametric faults not
    detected
  • multi-bit 9 out of 36 parametric faults not
    detected
  • Both have detected all open/short faults
  • Increasing test time (4x)
  • 1-bit 7 out of 36 parametric faults not detected

24
Analysis (2) Comparator Offset
Small influence on the distance for usual values
of offset.
25
Analysis (3)
  • smallest sampler and signal generator (minimal
    additional analog area)
  • minimum performance degradation
  • (constant load, no switches or muxes)
  • enables the observation of several test points
  • allows reuse of resources in a SoC environment.
  • low cost

26
Conclusions
  • A PSD-based test for analog circuits using 1-bit
    DAC and ADC was presented
  • Small degradation of the test when comparing to
    the multi-bit case
  • Trade-off analog area x test time
  • Lower test time at the system level because of
    parallelism
  • Further work non-linear systems.
Write a Comment
User Comments (0)
About PowerShow.com