P. 1

1
Fully Parallel Learning Neural Network Chip for
Real-time Control

• Jin Liu
• Advisor Dr. Martin Brooke
• Dissertation Defense Examination
• May 25th, 1999

2
Overview

• Introduction to Neural Network (NN)
• Review of NN Hardware Implementations
• Random-Weight-Change Algorithm and Chip
• Hardware Test and Modification
• Software Simulation on Combustion Control
• NN Chip Control of Simulated Combustion
  Instability
• New Generation of the NN Chip
• Conclusion and Future Work

3
A Neuron
w1
In1 In2 In3
w2
Out
w3
Out f ( In1w1 In2 w2 In3w3)
4
A Neural Network
A Neuron
Weights are updated according to
learning algorithm.
In1
Out
In2
In3
5
Review of Neural Network Hardware

• Serial Digital 1
• Partially Parallel Digital 2
• Fully Parallel Digital 3
• Fully Parallel Analog 4

1 Gensuke Goto, Tomio Sato, Masao Nakajima, and
Takao Sukemura, "A 54 x 54-b Regularly Structured
Tree Multiplier", IEEE Journal of Solid-state
Circuits, Vol. 27, No. 9, September, 1992. 2
Moritoshi Yasunaga, Noboru Masuda, Masayoshi
Yagyu, Mitsue Asai, Katsunari Shibata, Mitsue
Ooyama, Minoru Yamada, Takahiro Sakaguchi, and
Masashi Hashimoto, "A Self-Learning Digital
Neural Network Using Wafer-Scale LSI", IEEE
Journal of Solid-state Circuits, Vol. 28, No. 2,
February, 1993. 3 S. Neusser and B. Hofflinger,
"Parallel Digital Neural Hardware for Controller
Design", Mathematics and Computers in Simulation,
Vol. 41, Pp. 149-160, 1996. 4 Kenichi Hirotsu
and Martin Brooke, An analog neural network chip
with random weight change learning algorithm,
Proceedings of the International Joint Conference
on Neural Networks, pp. 3031-3034, October 1993.
6
Time for One Forward Propagation
Network Size
Implementations
(Time Number of Gate Delay)
7
Plot
8
Area
Network Size
Implementations
(Area Number of Transistors)
9
Plot
10
Efficiency
11
Area and Time Requirement for 0.35-mm CMOS Process
12
Estimation of the Speed of 70-nm CMOS Process
The 31 Stage Ring Oscillator Frequency 497 MHz
(Gate Delay 0.0649 ns)
Frequency
Process
13
Area and Time Requirement for 70-nm CMOS Process
14
Learning Algorithm - Random Weight Change (RWC)
Target
Starting Point
15
Random-Weight-Change Chip (Modified)
16
Chip Architecture - Block Diagram
17
Cell Schematics
Cell
18
Weight Updating
19
Multiplier Function
20
Clocking Scheme for Learning
21
Hardware Tests

• Shift Registers for Shifting Random Numbers
• Weight Increasing and Decreasing
• Biasing for Multiplier to Give Correct Transfer
  Function
• Training One Weight to Desired Value
• Training Two-input/One-output Network as an
  Inverter

22
Test Setup
23
Weight Updating
24
Multiplier
25
Training One Weight
To train one weight so that the neuron gives a
desired output value, given a fixed input
26
Capacitor Coupling Trial
27
Training with 01/10 Pairs
28
Training with Random Numbers
29
Two Input Inverter
To train a two-weight network, the desired output
inverses one of the inputs, with the other as a
reference voltage
0 1v 1 2v
30
Computer Collected Data
31
Error Signal
32
Initial Learning Process
33
More Data for Different High/Low Values
0.5-1.5
34
Continuously Adjusting Process
35
Summary of Preliminary Hardware Test

• The RWC chip learned to implement an inverter
  function, within around 140 iterations.
• It maintains the desired performance by
  continuously adjusting on-line.

36
Combustion Instability Control -Simulation
Results Review

• Simulated Neural Net and Combustion
• One-frequency Results
• Multi-frequency Results
• Parameter Variation Results
• Added Noise Results

37
Simulation Setup
38
One Frequency Result
f 400Hz b ?
39
One Frequency Plant without Control
40
Two-Frequency Results
f 400Hz 700Hz b ?
41
Parameter Variation Results
f 400-600Hz z 0-0.008 b 1-100
42
10 Added Noise Results
f400Hz z0.005 b1
43
Neural Network Chip Control of Combustion
Instability
44
Experiment Setup
45
The Test Box
46
Experimental Result
f 400Hz z 0.0 b 0.1
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More Results
48
More Results
49
Details of Initial Oscillation Suppression
Error Decreases
50
Details of the Continuously Adjusting Process
Error Decreases
Error Increases
51
Experiments with Longer Running Time
52
Experiments with Bigger Damping Factorz0.001
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Experiments with Bigger Damping Factorz0.002
54
Summary of NN Chip Control of Simulated
Combustion Instability

• The NN chip can successfully suppress the
  combustion instabilities within around 1 sec.
• The NN chip continuously adjusts on-line to limit
  the engine output to be within a small magnitude.
• I/O card delay and engine simulation delay
• 30 times longer than real time
• Weight leakage
• Fixed learning step size

55
Improved Neural Network Chip in 0.35- mm Process

• Seven Time More Neuron Cells
• Two layers
• Each layer has 30 inputs instead of 10
• Totally 720 neurons instead of 100
• Adaptive Learning Step Size
• Capacitor charge sharing scheme
• Current charging and discharging scheme
• Partitioned Error Feedback
• Synchronized Learning, without stopping the clocks

56
New Chip
57
Chip Architecture - Block Diagram
58
Cell Schematics
Cell
Cell
59
Full Chip Spice Simulation after Parasitic
Extraction

• Shift Register
• Weight Updating
• Current Outputs at Pads
• Clocking Scheme

60
Shift Register
X1ms First 0 to 1 at sh_in
X15.4ms First 0 to 1 at sh_out_end 720 cycles of
delay
X1.48ms First 0 to 1 at sh_out_1r 24 cycles of
delay
61
Weight Updating
Shifted in voltage
Weights
62
Output Currents at Pads
63
Clocking Scheme for Learning
One clocking cycle is 20 ms
64
Conclusion

• Extensive software simulations to provide a
  solution for real-time control using the RWC
  algorithm, with direct feedback scheme
• Successful application of the analog neural
  network chip to control simulated dynamic,
  nonlinear system
• Improved chip resulted from the extensive
  hardware experiments
• Automated test method and system

65
Future Works

• Acoustic Oscillation Suppression
• Test of the New Chip
• Real Combustion System Control
• Third Generation Chip (Million Weights)

66
Acoustic Oscillation Setup