The CCB and Related Trigger Control Issues

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The CCB and Related Trigger Control Issues
B. Paul Padley Rice University
2
TTC distribution to Partitions
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TTCvi and TTCvx
TTCvi delivers (under VME control) Channel A
(L1ACC) and Channel B (commands and data)
signals to the TTC transmitters for multiplexing,
encoding, optical conversion and
distribution. TTCvx multiplexes and encodes A
and B channels and transmits the resulting
modulated signal to 4 optical channels. No VME
functions.
4
TTCvi and TTCvx
TTCvi
TTCvx
We have had these at Rice for some time, but have
not been able to get hold of a TTCrx until
November
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Crate with TTCrx
B I T 3
T T C vx
T T C vi
C C B99
TTCrx is an ASIC mounted on a small mezzanine
board connected to CCB. Recovers 40Mhz clock,
commands and broadcast data.
T T C rx
VME 9U crate
6
CCB 99 with TTCrx

• TESTED AT RICE in NOVEMBER00
• Electrical connections between TTCvi andTTCvx
  and optical connection between TTCvx and TTCrx
  mounted on CCB99 prototype
• 40Mhz clock and L1ACC recovery from the TTCrx and
  their distribution at the CCB99
• TTCrx programming (control, fine and coarse delay
  registers) from the TTCvi over optical cable
  (write only) and decoding of selected broadcast
  commands

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Two Fast Command Modes

• Fast commands are sent via TTC chan. B
• Two Types are possible
• Broadcast commands
• 6 bits (upper two called user)
• Addressed Commands
• 8 bits sub-address and 8 bits data
• Can be sent to a specific TTCrx (ie. Specific
  peripheral crate)
• During Normal running we (EMU) can not send
  fast command data
• During stand alone running can send what we
  please

6 Broadcast bits and 8 data bits available on
backplane
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Normal Running Commands

• So far the list of Normal Running Commands are
• L1 Reset
• hard_reset
• Start Trigger
• Stop Trigger
• Test Enable
• Private Gap
• Private Orbit
• BX0
• Bunch Counter Reset

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Stand Alone Commands

• Current List from CCB specification

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Peripheral Clock and
Control Board
CCB99 CCB2001
Connections to TMB, DMB,
MPC Cables
Backplane Interface logic
LVDS LVDS
GTLP Number of serviced modules
6 19 Total number
of signals to modules 24 (out)
129 (in/out) Interface to TTC
old TTCrx new
TTCrx Fast control bus signals
no
yes Reloading protocol signals
no yes Special
purpose bus signals no
yes FPGA Technology
Altera 10KA Altera
10KA
(on
mezzanine card)
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Clock Distribution

• 40Mhz clock comes from one of three sources
• TTCrx (Clock40Des1)
• on-board quartz oscillator
• front panel (ECL)
• Doesnt pass through any PLD/FPGA before
  distribution to backplane drivers
• Can be adjusted (in steps of 1 ns) individually
  to each slot in crate (programmable over VME)
  (using Rad Hard PHOS4 chip from CERN)

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J1
TTCrx MEZZANINE CARD
OPTICAL CABLE FROM TTCvx
BUFFERS
53
58
ECL INPUTS
MEZZANINE CARD WITH PLD
36
110
CUSTOM BACKPLANE
BUFFERS
BUFFERS
ECL OUTPUTS
9U 400 MM BOARD
CLOCK AND CONTROL BOARD BLOCK DIAGRAM
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Data Bus

• We are putting broadcast and some addressed data
  bits on backplane busses.
• Programmability will be in the other cards
  interpreting the bussed signals.
• Some Signals (L1A, BX0, for example) derived and
  on bus
• This allows us to possibly hardwire (fuse
  technology) the CCB with a Rad Hard device

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Rad Hard Possibilities

• Radiation hardness is a crucial issue for the CCB
  and we worry we may have to go to a rad hard fuse
  technology. (other boards get their reset from
  CCB, but where does the CCB get a reset from?)
• FPGA on mezzanine card so can replace with Rad
  Hard chip in future
• Logic is designed to fit a Rad Hard device (such
  as available from Actel)

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Status as of 3/19/01

• Main board schematic completed 80
• Mezzanine card schematic completed 70
• PLD design completed 80
• Updated manual is available on the web

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Plans

• Board Layout - April
• Board Fabrication - May
• Testing and Debugging - JuneJuly
• On Schedule for Aug 1 Milestone