How to plan on project work?

1
How to plan on project work?

• An attempt to consolidate your thought to gear up
  project activities

2
Major grade Projects

• Suggested areas
• MP3 decoder implementation using codesign
  approach
• Use of HDLC core and design Ethernet interface
• Application specific codesign (two projects)
• Check if there is another codesign problem

3
Alert to make use of..

• Suitable model if not given, may develop one
• specification use appropriate language(s)
  including HDL, state diagram, C or its class
• Target architectures controller and/or FPGAs or
  both
• Partitioning and simulation

4
Make use of ...

• Core open source cores available for some
  building blocks
• Implementation only after making sure that the
  design is validated

5
Suitable models

• Consider tool(s) that you are accessible to
• may borrow open tools if one is available
• analyze why certain model is better than other
  for your application
• Discussions open

6
Languages

• Believe that most designs require C, Verilog or
  VHDL as building components
• Estrel is required if Polis is in use
• For cosimulation using C and Verilog VerilogPLI
  is required for interfacing between the language.
• Complex designs require multi-language interfaces

7
Target Architectures

• A controller such as Motorola 68K class as
  supported by the Ptolemy (?).
• FPGAs Xilinx 4000 series (4010, 4028), Spartan
  (2 pieces), Vertex board (one) capable of
  handeling 800K gates design.
• Vertex board is capable of interfacing several
  devices such as monitor, network, audio/video and
  parallel ports

8
Target architectures

• Stand alone FPGA boards small commercial boards
  available with serial or parallel ports for
  download
• can devise your own FPGA board too to go with
  other design but know the pin details from the
  data book in the lab, wire-wrap.
• DSP board TMS320671 is one of the highend DSP
  board from Texas Instruments.
• Capable of programming in C,
• run several benchmarks from open sources
• full supported software tools available

9
Partitioning

• Functional
• May use GCLP algorithm for your problem
• can modify the algorithm, choose varieties of
  partitioning combinations and check for the best
• verification cosimulation, emulation,
  Ptolemy/Polis,
• Library important to know the hw and sw
  implementation overhead either from given sources
  or build one
• Research problems

10
Cores

• Several open sources
• PCI, HDLC are free licences to the lab, can look
  for other sources too
• look for benchmarks on available cores
• Level cores are mostly in gate level, some times
  - behavioral level is better for making changes,
• can use existing codes on interface such as
  serial/parallel may not reinvent the wheel
• Share the cores too.

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Implementation

• Complete the projects only after combining hw
  and sw in its implementation.
• Results
• timing details for each possible partitioning
  effects and the optimum result seen by you
• area information from synthesis level
  verification
• suitable reports with all developed codes and
  references

12
Actions

• MP3 decoder find suitable algorithms
• Look at the Vertex platform and DSP hw/sw details
• search DSP benchmarks (ask Rahul)
• Lay out a plan based on todays discussions and
  approve it from instructor.
• Let us know if you need any resources for your
  projects
• Use your lab time wisely.

13
Discussions

• Open for questions and suggestions
• Will continue until semester end