Register Transfers

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Register Transfers

• 55032 - Introduction to Digital Design

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Large System architecture

• Large digital systems typically partitioned into
• Datapath
• Many registers, lots of Combinational Logic
• Moves / processes system data
• Operation specified by control word (from CU)
• Control Unit
• Many states and inputs
• Specifies what DP does next
• Decisions made based on DP status information

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Large System Block Diagram
Control Unit
Datapath
Control Inputs
Data Outputs
Control
Status
Control Outputs
Data Inputs
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Register Transfer

• The movement of data stored in registers and the
  processing performed on the data are referred to
  as Register Transfer Operations
• Register Transfer Language (RTL) captures
  register transfers and its components of
• The registers within the system
• The operations performed on system data
• The control that defines the sequence of operation

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Microoperations

• Each register has a set of elementary operations
  it can do
• E.G. Load, Increment, Shift, etc.
• The combination of elementary register ops and
  combinational functions define simple system
  operations
• These are the Microoperations of the system
• Usually performed in a single clock cycle
• Sequence of ?-ops specified by control unit

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Register Transfer Notation

• General form of register transfer expression
• Destination Register ? Information source
• where ? is the replacement operator
• Destination register contents is replaced by
  source information
• Ususally done at the next clock
• Transfers may be conditional
• Condition Dest. ? Source

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Register Transfer Notation

• Registers denoted by uppercase letters
• E.G. A, PC, R0, SP
• Individual FFs indexed as either big-endian or
  little-endian (need to define which)
• BIG MSB is 1, LSB is n
• LITTLE LSB is 0, MSB is n-1
• Register parts referred to by H, L or bit range
• PC(H), PC(L), IR(158), IR(70)

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Register Transfer Notation

• Register transfer source information may be
• A single source register
• External input data
• Results of combinational logic operation
• E.G.
• R0 ? R1
• IR ? MAR (memory read at loc AR)
• PC ? PC 1

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Register Transfer Operations

• The microoperations is a system generally
  classified into four types
• Transfer - moving data from register to register
• Arithmetic - signed and unsigned arithmetic
• Logical - bitwise and, or, not, etc.
• Shift - shifts, rotates, etc.
• See table 7-2 in text for correspondence between
  RTL and VHDL

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Arithmetic Microoperations

• Basic addition and subtraction
• Signed and unsigned
• Negative number representation to be used must be
  stated
• Increment and decrement
• Comparison (output is true or false!)
• Multiplication might be included
• Very complex combinational logic
• Division is rarely included

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Logical Microoperations

• Include the bitwise AND, OR, NOT logical
  operations
• You may see new symbols used in RTL
• AND - ?
• OR - ?
• These are needed to reduce confusion between
  arithmetic and logical operations
• Logical ops used for bit set, clear masking

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Shift Microoperations

• Dont have standard operator symbols
• You should include a key for anything outside of
  the authors definition
• Include left and right shifts and rotates
• Logical and arithmetic shifts
• Must properly handle sign bit, overflow cond.
• Shift microoperations do not necessarily imply a
  shift register
• R1 ? sr R2 (no SR needed here)

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Transfer Operations

• Each is simple complexity results from designing
  hardware to perform all defined transfers for
  each register
• Many data sources (need to select)
• Different control for each source
• Selection of the data source may be via
• Multiplexers
• Data bus

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Multiplexer-based Transfer

• You have a limited number of local data sources
• E.G.
• K1 R1 ? R3
• K2 R1 ? R1 R2
• Two sources are defined use a 2 to 1 mux
• Small combinational function need to translate
  the K1 and K2 controls to the mux select and
  register load control signals

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Multiplexer-based Register Transfer
General Circuit Pattern
Dest. Reg.
MUX
Src 1
Src 2
EN
Src n
Clk
select
Comb. Logic
Controls
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Multiple Register Transfers with MUXes

• Systems usually have multiple destination
  registers, each with multiple sources
• Common to have multiple reg. transfers at the
  same time
• Designer has some choice of implementation
• Use separate multiplexer for each destination
• Use a shared multiplexer for all dest. Registers
• Perform the source selection function with
  three-state outputs

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Dedicated Multiplexers
MUX
Reg. A
REGB
Advantage is multiple register transfers can take
place at the same time.
REGC
REGD
LDA
SELA
MUX
Reg. B
REGA
REGC
REGD
LDB
SELB
MUX
Reg. C
REGA
REGB
REGD
Disadvantage is lots of hardware is needed.
LDC
SELC
MUX
Reg. D
REGA
REGB
REGC
LDD
SELD
Clock
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Shared Multiplexer
Reg. A
Advantage is less hardware is needed.
LDA
Reg. B
MUX
REGA
REGB
LDB
REGC
Reg. C
REGD
Disadvantage is only one register transfer source
can be selected at a time.
SEL
LDC
Reg. D
LDD
Clock
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Selection via Three State Outputs
Reg. A
ENA
LDA
Now the sources can be distributed only the
three state bus needs to go from source to
source Only one source can be selected at a time
but much less wire is needed.
Reg. B
ENB
LDB
Reg. C
ENC
LDC
Reg. D
END
LDD
Clock