PI: ARAVIND DASU

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Integrated Software Environment to Design
Polymorphic Fault tolerant Processors for Command
and Control functions on RadHard FPGAs Year 2 of
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• PI ARAVIND DASU
• GRAD STUDENTS JONATHAN PHILLIPS
• ARVIND SUDARSANAM
• ROB BARNES
• AISRP WORKSHOP
• MAY 7TH 2008

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Motivation

• Increased complexity of on-board mission
  planners/GNC apps challenge the traditional
  workhorse of space based computers embedded
  microprocessor
• So, are FPGAs the new platform?
• Encouraging and Emerging companion technologies
• Dependable multiprocessor system
• NASA sponsored Honywell, U. Florida
• Multi-FPGA system
• Carbon Nano Tube based FPGAs
• NRO NASA effort

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The caveat of FPGAs

• FPGAs are only configurable fabrics
• Have little or no smarts in terms of architecture
• Acceleration or adaptable hardware features are
  only as good as the design that is mapped onto
  them
• Responsibility of deriving smart architectures
  resides with designer
• Tedious process
• Design space for circuits can get too large

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Our Design Methodology to make FPGAs more user
friendly

• Components of the design environment
• Template for hardware exploration
• Application specific Partial C 2 FPGA compiler
• Fault tolerance/mitigation design methodology

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On-board applications (present future)

• Command Control
• Scheduling
• Guidance
• Navigation
• Control etc
• Data processing communication
• Compression
• Classification etc.

(Iterative Repair using Simulated Annealing)
(Kalman filters)
SATH
KFTH
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Proof of Concept SATHSimulated Annealing To
Hardware tool flow

• Step 1
• Identifying a template in hardware suitable for SA

Temperature ? INITIAL_TEMP Generate initial
solution Compute score of initial solution While
temperature gt STOP_THRESHOLD copy next_solution
? current solution alter modify
next_solution evaluate compute score of
next_solution accept probabilistically accept
next_solution adjust_Temperature

• Data dependency
• Limits temporal parallelism
• Complicates exploring spatial parallelism

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Hardware Template for SA
PDR

• Various flavors of alter and evaluate functions

• Flexible Functionality
• Exactly same as software
• Flush pipeline
• Better than software with speculation
• Allow data processing

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Prototype Implementation Results
TSP using SA 100 cities
TSP-P
IR using SA
A Coarse-grain Pipelined Architecture for
Accelerating Iterative Repair-Type Event
Scheduling on SRAM-FPGAs, submitted for review
to the IET proceedings on Computers and Digital
Techniques 2008.
Deriving FPGA Based Custom Soft-Core
Microprocessors for Mission Planning Algorithms,
Aravind Dasu and Jonathan Phillips. 21st annual
AIAA Small Sat conference 2007.
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Step 2 Partial C 2 FPGA Compiler

• Runs on a design space explorer that trades-off
  area and latency for varying levels of
  concurrency
• Cost of parallelism different for each function
  processor stage
• Example 1 Copy stage can severely affect BRAM
  usage
• Example 2 Evaluate stage can affect
  Slices/multiplier cores usage

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Area estimation ? Frequency estimation ?
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First set of results from the DSE
100 city TSP problem
Still being refined Bugs being ironed
out Expected demo in July/August
Same area on V4sx35 and xqr2v6000
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Progress on KFTHKalman Filter to Hardware tool
flow
Vector processor hardware template Systolic Array
hardware template
Hardware/Software Co-designed Extended Kalman
Filter on an FPGA, Rob Barnes, Aravind Dasu,
accepted to the international conference on
Engineering of Reconfigurable Systems and
Algorithms 2008.
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Broader Impact on optimizing the silicon
compiler Context adaptable cores
Methodology to derive context adaptable cores
for FPGAs under review with the IET proceedings
on Computers and Digital Techniques
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Conclusions

• Future work (year 3)
• Integrate support for multi-level loops and
  conditional branching in the Partial Compiler
  (SATH KFTH)
• Compare tool performance against
  opensource/available C to gates tools
• HandelC, ImpulseC, SystemC
• Fault tolerant design methodology for both SATH
  and KFTH
• Compare against Xilinx TMR

We thank NASA and the AISR program for their
support
Resonance from the Industry to our work Micron
Technology has started funding work related to
Fault mitigation Mathstar Inc. has started
funding work related to the Partial C 2 FPGA
compiler Xilinx has donated all the necessary
tools (ISE, EDK, PlanAhead, TMR) Resonance from
State of Utah The Utah Centers of Excellence
Program is funding work related to silicon
compilers
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Step 3 Its gotta work in space SEU protection
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Exploring DMRH Double modular redundancy with
Hold
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Example SEU protected Accept module

• Unprotected divider, comparator, and I to F
• Slices 1592
• TMR (unprotected3)
• Slices 4776
• Area Increase 200
• DMRH
• Total Slices 3386
• Voter Slices 138
• Comparator Slices 64
• Cfg. Frames 1540
• Penalty On Fault 30.8ms
• Area Increase 113