EXPRESSION: An ADL for system Level Design Exploration

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EXPRESSIONAn ADL for system Level Design
Exploration
P.Rama Sudhakar 4th Aug 99 IIT Delhi , India.
Data source EXPRESSION A Language for
Architecture Exploration through
Compiler/Simulator Retargetability ", DATE 99, by
Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh
Khare, Nikil Dutt and Alex Nicolau
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Architecture Level Design

• new processor architectures (DSP, RISC,
  VLIW, ASIPs...)
• need ability to explore across different types of
  architectures.
• novel memory organizations and hierarchies (DRAM,
  Buffers,Register files..)
• need ability to match processor with memory
  configuration.
• Software-issues dominate
• rapid software toolkit generation (compiler,
  simulator, debugger,...)

Need a mechanism to describe the architecture -
ADL
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Role of an ADL in Embedded System Design
Processor Evaluator
Architecture Template (Architecture description )
Described in ADL
Partitioning
System Integration
Rapid design space exploration
Quality tool-kit generation
Design reuse
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Outline

• Architecture Description Languages (ADLs)
• EXPRESSION Organization
• EXPRESSION Description
• Example
• Modified Design Flow
• Summary

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Ideal features of an ADL

• Specify a wide variety of architecture classes
  (VLIWs, DSP, ASIPs)
• Specify novel memory organizations
• Specify pipelining mechanism
• Specify constraints
• Specify detailed instruction-set information
• Represent modification to the target
  architecture for DSE
• Easily understandable
• Support automated SW toolkit generation
• exploration quality SW tools (performance
  estimator, profiler, )
• production quality SW tools (cycle-accurate
  simulator, memory-aware compiler..)

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Various ADLs

• Behavior-Centric ADLs (primarily capture
  Instruction Set (IS))
• nML, ISDL, ...
• good for regular architectures, provides
  programmers view
• tedious for irregular architectures, hard to
  specify pipelining, implicit arch model
• Structure-Centric ADLs (primarily capture
  architectural structure)
• MIMOLA, ...
• can drive code generation and architecture
  synthesis, can specify detailed pipelining
• hard to extract IS view
• Mixed-Level ADLs (combine benefits of both)
• MDes,
• contains detailed pipelining information
• most are specific to single processor class
  and/or memory architecture
• most generate either simulator or compiler but
  not both

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EXPRESSION Organization

• EXPRESSION has two major components
• Description of the structure of the architecture
• Components Units (e.g., alu), Storages (e.g.,
  latches), Ports, Connections
• Pipeline and datapath information
• Memory hierarchy
• Description of the instruction-set of the
  architecture
• Syntax and Semantics of the operations
• Format of the instruction (e.g. bit-width)
• Information needed by compiler optimizations

EXPRESSION tightly integrates the structural and
instruction-set descriptions, reducing complexity
and improving readability/usability
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EXPRESSION Description

• Describing structure in EXPRESSION
• Library based approach
• Built-in, parameterized processor and memory
  components
• cache (line-size, set-size, etc), main-memory
  (size, width, storage-type, etc)
• User specifies connectivity using high-level
  constructs
• Pipeline connectivity, Datapath connectivity
• Describing instruction-set in EXPRESSION
• Hierarchical approach to avoid repetition
• Operations are composed of fields (e.g., opcode,
  arguments).
• Operations (and fields) are grouped according to
  attributes (e.g., semantics, type)

Constraints on parallelism between operations are
automatically generated from the structure and
instruction-set description.
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Example Architecture in EXPRESSION
Section 1 Operations Specification (OP_GROUP
alu_ops (OPCODE ADD (OP_TYPE
DATA_ OP) (OPERANDS (SRC1 g1) (SRC2
g1) (DST g2)) (BEHAVIOR
DSTSRC1SRC2) ) ) (OP_GROUP pmove1_ops
(OPCODE pmove1 (OP_TYPE DATA_OP)
(OPERANDS (SRC1 g4) (DST g4) )
(BEHAVIOR DSTSRC1) ) ) (VAR_GROUP
(g1 RFX) (g2 RFA RFB)
(g3 RFY) (g4 X_mem) ) -------

Cross Box
C1
Describes the Instruction Set of the Processor
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Instruction Description
The instr has 4 slots (alu, mult and 2
parallel moves) (INSTR (WORDLEN
32) (SLOTS
((TYPE DATA ) ( BITWIDTH 8) (UNIT ALU))
((TYPE DATA ) ( BITWIDTH 8) (UNIT MULT))
((TYPE DATA ) ( BITWIDTH 8)
(UNIT AGU1)) ((TYPE DATA ) (
BITWIDTH 8) (UNIT AGU2)) ) )
Operation Mappings (OP_MAPPING (
(GENERIC (mult src1 2
dst)) (TARGET ( add src1
src1 dst)) ) )
Instruction
Slot1
Slot2
Slot3
Slot4
Captures parallelism available in the instruction
Captures architecture-specific optimization
information
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Architecture Section
Section 2 Describes each RT-level component
in the architecture Components Pipeline units,
Functional units, Storage elements, Ports,
Connections, Buses Attributes (optional )
Subcomponents, Latches, Ports, Connections,
Opcodes, Timing, Capacity etc.., //Subtype
declarations (SUBTYPE UNIT FetchUnit DecodeUnit
ExUnit AGUUnit ) (SUBTYPE STORAGE RegFile
Memory) (SUBTYPE CONNECTION Bus CBox)
(FetchUnit Fetch (LATCHES
fetDecLatch) (PORTS
fetProgMemPort) (CAPACITY 4) )
(ExecuteUnit ALU (LATCHES
decExLatch1) (OPCODES alu_ops) )
//Register files (RegFile RFA( )
(CONNECTIONS C1 ALU_RFA) ) (RegFile RFX( )
(CONNECTIONS C3 RFX_ALU RFX_Mult) )
// Memory Components (Memory X_mem()
(CONNECTIONS C5) ) // Busses (Bus X_bus( )
( CONNECTIONS C1 C3 C5 CrossBox) ) // CBox
(CBox CrossBox( ))
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Pipeline and Data-Transfer Paths Description
Pipeline description provides a mechanism to
specify the units which comprise the pipeline
stages Data-Transfer paths description provide a
mechanism for specifying the valid data transfers
// Pipeline paths (PIPELINE FETCH DECODE EX)
(EX ALU Mult AGU1 AGU2 ) //
Data-transfer paths (DTPATHS (TYPE UNI
(RFA X_bus C1) (RFB Y_bus C2)
(RFX X_bus C3) (RFY
Y_bus C4) (X_mem X_bus C5)
(Y_mem Y_bus C6) (X_bus Y_bus
CrossBox) ) (TYPE BI (RFX ALU
RFX_ALU1) (RFX ALU RFX_ALU2)
(RFX Mult RFX_Mult1) (RFX
Mult RFX_Mult2) (ALU RFA ALU_RFA)
(ALU RFB ALU_RFB)
(Mult RFY ALU_RFY) ) )
Fetch
Decode
Execute
Mult
AGU1
AGU2
ALU
Describes the net-list of the processor
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Memory Subsystem
Describes the attributes of each storage
component (STORAGE_PARAMETERS
(RFA (TYPE REGFILE
(SIZE 2)
(WIDTH 24) )
(L1_X_cache (TYPE
D_CACHE) (SIZE 64)
(LINE 48)
(ASSOCIATIVITY 2)
(ADDRESS_RANGE 256 767)
(ACCESS_TIMES 1) )
(X_mem (TYPE
DRAM) (SIZE 512)
(WIDTH 24)
(ADDRESS_RANGE 256 767)
(ACCESS_TIMES 10) ) )
L1_sram
X mem
CPU
RFA
RFB
L1_X_cache
Y mem
RFX
RFY
L1_Y_cache
Describes the properties of the components in the
memory subsystem
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Architectural Changes

• adding a bus and 2 connections
• splitting a register file
• adding a connection

• Range of architectures specified in EXPRESSION
• VLIW Texas Instruments TMS320C62x processor
  
• DSP Motorola DSP 56000

complex pipeline , multiple execution units
Bus based architecture, Distributed register
files and complex addressing modes
We can use EXPRESSION for architecture
description in our design flow
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Modified Design Flow
Architecture Template (EXPRESSION)
(Expression)
C Specification
SUIF Compiler Passes
Template Translator
Spec. IR (ESIR)
Template IR (ESIR)
Processor Evaluator
Partitioning
Proc suitability metrics
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Interaction between EXPRESSION and other tools
Project at University of California , Irvine
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Summary

• Presented EXPRESSION, a new ADL for
• rapid Design Space Exploration (DSE)
• high-quality software toolkit (compiler/simulator)
  generation
• EXPRESSION
• combines both behavioral and structural
  information
• eliminates redundancy, reduces possibility of
  error
• able to extract constraint information from
  specification
• enables design reuse

Example demonstrate usefulness of EXPRESSION in
architecture exploration