A Methodology for Validation of Microprocessors using Equivalence Checking

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A Methodology for Validation of Microprocessors
using Equivalence Checking

• Prabhat Mishra, Nikil Dutt
• Center for Embedded Computer Systems
• University of California, Irvine, USA
• May 30, 2003

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Outline

• Motivation
• Architecture Description Language (ADL)
• The EXPRESSION ADL
• ADL-driven Validation Framework
• A Case Study
• Summary

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Motivation

• Shrinking time-to-market, short product life ..
• Reduce design time for embedded processors.
• Functional verification is a major contributor
• Existing validation approaches
• Simulation based approaches
• Formal techniques
• A significant bottleneck
• Lack of a golden reference model
• Study the feasibility of
• Architecture Description Language (ADL)

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Traditional Validation Approach
Architecture Specification (English Document)
Specification
Model Checking
Verification
Formal
Abstracted Design
Implementation
Abstraction
Simulation
RTL Design
Lack of an golden reference model
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Outline

• Motivation
• Architecture Description Language (ADL)
• The EXPRESSION ADL
• ADL-driven Validation Framework
• A Case Study
• Summary

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ADL-driven Design Space Exploration
ADL Architecture Description Language
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Architecture Description Languages

• Behavior-Centric ADLs
• ISPS, nML, ISDL, SCP/ValenC, ...
• primarily capture Instruction Set (IS)
• good for regular architectures, provides
  programmers view
• tedious for irregular architectures, hard to
  specify pipelining
• Structure-Centric ADLs
• MIMOLA, ...
• primarily capture architectural structure
• specify pipelining drive code generation, arch.
  synthesis
• hard to extract IS view
• Mixed-Level ADLs
• LISA, RADL, FLEXWARE, MDes, EXPRESSION,
• combine benefits of both
• generate simulator and/or compiler

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Outline

• Motivation
• Architecture Description Language (ADL)
• The EXPRESSION ADL
• ADL-driven Validation Framework
• A Case Study
• Summary

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The EXPRESSION ADL

• Captures programmable embedded systems
• Processors and memory subsystem
• Structure, behavior and mapping
• Pipeline and data-transfer paths
• Generates software toolkit automatically
• Enables early design space exploration
• DLX, Hitachi SH3, TI C6x, MIPS R10K, ARM,
• Public Release http//www.cecs.uci.edu/express
• Exploration of MIPS R4000 architecture
• Instruction-Set Architecture (ISA) Exploration
• Pipeline Exploration
• Memory Subsystem Exploration

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Outline

• Motivation
• Architecture Description Language (ADL)
• The EXPRESSION ADL
• ADL-driven Validation Framework
• A Case Study
• Summary

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ADL-driven Validation Framework

• Steps
• Specify in ADL
• Generate RTL
• Check equivalence

Hardware Model
Different
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Outline

• Motivation
• Architecture Description Language (ADL)
• The EXPRESSION ADL
• ADL-driven Validation Framework
• ADL Specification
• Synthesizable HDL Generation
• Equivalence Checking
• A Case Study
• Summary

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ADL Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
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ADL Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
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ADL Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
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ADL Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
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ADL Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
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ADL Specification of the DLX Processor
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
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ADL Specification of the DLX Processor
Structure
Behavior
(OPCODE ADD (OPERANDS (SRC1 rf) (SRC2 imm)
(DEST rf)) (BEHAVIOR DEST SRC1 SRC2)
(FORMAT ) )
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ADL Specification of the DLX Processor
Structure
Behavior
(OPCODE ADD (OPERANDS (SRC1 rf) (SRC2 imm)
(DEST rf)) (BEHAVIOR DEST SRC1 SRC2)
(FORMAT ) )
Mapping
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Outline

• Motivation
• Architecture Description Language (ADL)
• The EXPRESSION ADL
• ADL-driven Validation Framework
• ADL Specification
• Synthesizable HDL Generation
• Equivalence Checking
• A Case Study
• Summary

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ADL-to-HDL

• ADL-to-HDL approaches
• MIMOLA, LISA
• Suitable for a class of architecture
• Goal generate HDL for wider range
• DSP, VLIW, Superscalar, Hybrid
• Functional Abstraction
• Observations
• Similar computations (operand read, data write,
  )
• New computations can be composed of existing ones
• Define generic functions, sub-functions
• Compose functions to create new architecture

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Functional Abstraction

• Defined generic functions and sub-functions
• Structure of a generic processor
• functions for units (fetch, decode, issue,
  res-station,)
• sub-functions for computations (read, write, )
• Behavior of a generic processor
• functions for each operation (add, sub, mul, div,
  )
• Generic memory subsystem
• functions for each component (cache, SRAM, SB, )
• Generic controller
• Interrupts and exceptions
• DMA, Co-processors etc.
• Demonstrated on simulator generation (ISSS01)

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Example1 Generic Fetch Unit

• FetchUnit ( read per cycle n, res_Station size,
  ........ )
• address ReadPC()
• Instructions ReadInstMemory(address, n)
• WriteToReservationStation(Instructions, n)
• outInst ReadFromReservationStation(m)
• WriteLatch(decode_latch, outInst)
• pred QueryPredictor(address)
• If pred
• nextPC QueryBTB(address)
• SetPC (nextPC)
• else
• IncrementPC(x)

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Example2 Modeling of MAC Operation
MUL (src1, src2) return (src1 x src2)
ADD (src1, src2) return (src1 src2)
MAC (src1, src2, src3) return ( ADD ( MUL
(src1, src2), src3) ) )
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Synthesizable HDL Generation

• Developed VHDL models for generic functions and
  sub-functions.
• Generating HDL description of the processor
• Major components
• Instruction Decoder
• Data Path
• Control Logic
• Steps
• Read ADL description
• Choose appropriate models (structure).
• Compose using appropriate parameters (behavior).

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Step 1 Read ADL Specification
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Behavior
Mapping
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Step2 Compose Structure

• DLX ( .. )
• FetchUnit ( 4, 0, )
• .
• DecodeUnit ( )
• ..
• ..
• ..
• Controller ( )

Reservation Station size
Input/output ports
fetches
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Step 3 Compose Behavior

• DLX ( .. )
• FetchUnit (4, 0, , )
• -- No reservation station (instruction buffer)
  processing
• DecodeUnit (.)
• -- Use binary description and operation mapping
  to
• -- decide where to send the current operation.
• ..
• ..
• Controller ( . )
• -- Use control table to stall/unstall/flush the
  pipeline .

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Outline

• Motivation
• Architecture Description Language (ADL)
• The EXPRESSION ADL
• ADL-driven Validation Framework
• A Case Study
• Summary

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Experimental Setup

• The EXPRESSION ADL is used
• Reference Model
• RTL generated from the ADL specification
• Implementation
• 32-bit RISC DLX from University of Stuttgart
• http//www.eda.org/rassp/vhdl/models/processor.htm
  l
• Equivalence Checker
• Formality from Synopsys
• Running on a 296 MHz Sun Ultra-250 with 1024M RAM

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Results

• 32-bit Adder
• Reference carry-look-ahead adder
• Implementation ripple-carry adder
• Validation 4 seconds
• 32x32 Register File
• Reference structural description
• Implementation behavioral description
• Validation 432 seconds
• 347 seconds spent on elaboration
• 32-bit RISC DLX
• Reference model generation is guided
• Validation 397 seconds

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Summary

• Functional verification is a major contributor
• We propose a top-down validation approach
• Specify processor in EXPRESSION ADL.
• Generate synthesizable RTL from specification.
• Use generated RTL as golden reference model.
• Applied this method on a DLX processor
• Using equivalence checking
• Assumes implementation knowledge
• Future work
• Validation without implementation knowledge
• Apply on real-life architectures

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• Thank you!

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Traditional HW/SW Co-Design Flow
Design Specification
Estimation
HW/SW Partitioning
HW VHDL, Verilog
SW C
Synthesis
Compilation
Co-Simulation
Off-Chip Memory
Processor Core
On-Chip Memory
Synthesized HW
Interface
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ADL-Driven SOC Design Flow
Design Specification
ADL Specification
Estimation
HW/SW Partitioning
HW VHDL, Verilog
SW C
Synthesis
Compilation
Co-Simulation
ADL Architecture Description Language
Off-Chip Memory
On-Chip Memory
Processor Core
Synthesized HW
Interface
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Is Abstraction Possible ?

• Similarities
• Functional units, connected using ports,
  connections, and pipeline latches
• Memory consists of SRAM, DRAM, caches ..
• Differences
• Same unit with different parameters
• Same functionality in different unit
• New architectural features
• Defined generic functions, sub-functions and
  computational framework

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MIPS R10000 Architecture
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Generic Controller (MIPS R10000)
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Generic Controller
Pipeline Stages
Parallelism
Distributed Control
Centralized Control