Sample Problems

1
Sample Problems

• Framing
• Suppose that the pattern 10001 were to be used as
  a frame separator.
• Suggest a bit stuffing algorithm that will avoid
  sending data that looks like a frame separator.
• Using your algorithm, show the bits actually sent
  for the frame
• 100110001100001
• (Be sure to include frame separators before and
  after the frame)

2
Sample Problems

• CRC
• A CRC is constructed to generate a four bit frame
  check sequence. The generator polynomial is X4
  X3 1
• Draw the shift register circuit that would
  perform this task.
• Suppose that bits 1001101 are to be sent.
  Calculate the frame check sequence
• by long division
• using the shift registers
• Verify correct reception
• by long division
• using the shift registers
• Suppose that after transmission, the indicated
  bit is changed from 1 to 0. Using long division,
  show that the receiver will detect the error

3
Sample Problems

• Parity table / error correction
• Suppose that you are using row and column parity
  bits for a block that has 4 rows and 4 columns.
• Odd parity is used for each of the rows and
  columns. Parity is not determined for the parity
  row/column, resulting in a 24 bit block.
• A transmission that has a bit length not
  divisible by 16 is padded with 0s to the next
  largest multiple of 16.
• Determine the data sent for the following
  transmission
• 011100110011110011001111
• What is the error determination for each of the
  following blocks received
• 011100001100111110010100
• 110011010100001000011110

4
Solutions follow...
5
Solution Framing (1)

• Frame separator bit pattern 10001
• To avoid including a frame separator in the data,
  we want to avoid sending three 0 bits in a row,
  as this leads to the possibility of a 1 bit
  following the third 0 being interpreted as a
  frame separator.
• Therefore, after two consecutive 0 bits in frame
  data, add a 1 bit no matter what follows.
• Receiver will delete any 1 that follows two
  consecutive 0 bits.

6
Solution Framing (2)

• Frame separator bit pattern 10001
• Original data 100110001100001
• Stuffed data 1001110010110010011
• With frame separators
• 10001100111001011001001110001

add 1 after two consecutive 0s
7
Solution CRC (1)

• The generator polynomial is X4 X3 1.
• There are as many shift registers as the highest
  power of the variable in the generator
  polynomial.
• An XOR goes to the right of each non-zero
  coefficient in the polynomial, where the X4 is
  the loop-around feedback .

single bit shift left register
XOR
3
2
1
0
X4
X3
X0
Message bits
8
Solution CRC (2)
1110011 ------------ 11001
10011010000 11001......
-----...... 10100.....
11001..... -----.....
11011.... 11001....
-----.... 0010000.
11001. -----. 10010
11001 -----
1011

• The generator polynomial isX4 X3 1, so the
  bit pattern is 11001 .
• Add four zero bits to the message with a five-bit
  divisor
• When leading digit(s) are zero, bring down enough
  extra digits so that you have as many bits as the
  divisor, with the leading bit being one.
• When to stop when there are no more digits to
  bring down.
• CRC is last remainder, with leading zeros if
  needed.

9
Send 1001101
initial state, before first bit enters
0
0
0
0
1
0
0
0
1
after first bit shifted, before second bit enters
0
0
0
1
0
0
0
1
0
0
this line will be repeated on next slide
1
10
Send 1001101
repeated from previous slides last line
0
1
0
0
1
1
0
0
1
1
bits changed by XOR
1
0
1
0
0
1
1
0
1
1
first of the padding bits
0
0
1
0
this line will be repeated on next slide
0
11
Send 1001101 (padding)
repeated from previous slides last line
0
0
1
0
0
0
1
0
0
0
bits changed by XOR
1
0
0
0
0
1
0
0
1
0
CRC is whatever is left in the register when
there are no more padding bits
1
0
1
1
12
Correct reception
11100101 ------------ 11001
10011011011 11001......
-----...... 10100.....
11001..... -----.....
11011.... 11001....
-----.... 0010101.
11001. ------. 011001
11001 -----
0000

• Bits received, including CRC 10010111011
• Perform same division, but include actual CRC
  bits received.
• Remainder is 0000, so it is assumed that the
  message was received correctly.

13
Receive 10011011011
initial state, before first bit enters
0
0
0
0
1
0
0
0
1
after first bit shifted, before second bit enters
0
0
0
1
0
0
0
1
0
0
this line will be repeated on next slide
1
14
Receive 10011011011
repeated from previous slides last line
0
1
0
0
1
1
0
0
1
1
bits changed by XOR
1
0
1
0
0
1
1
0
1
1
first of the CRC bits
0
0
1
0
this line will be repeated on next slide
1
15
Receive 10011011101
repeated from previous slides last line
0
0
1
0
1
0
1
0
1
0
bits changed by XOR
1
0
1
0
1
1
1
0
0
1
Zero register means that message is assumed to be
correct.
0
0
0
0
16
Incorrect reception
1110100 ------------ 11001
10010011011 11001......
-----...... 10110.....
11001..... -----.....
11111.... 11001....
-----.... 011010..
11001.. -----.. 001111

• Bits received, including CRC 10010011011
• Perform same division, but include actual CRC
  bits received.
• Result is 1111, and since the remainder is not
  zero, there must be an error.

17
Block parity / Error correction

• Create blocks of 16 bits
• Determine odd parity for each row
• Determine odd parity for each column
• Read bits out by row, and send blocks of 24 bits.
• 011100011100111110010100
• 110011111100001000011100

18
Block parity / Error correction

• Determine that the third bit in the second row is
  in error, and should be corrected to a 1.

19
Block parity / Error correction

• Determine that there has been a multiple bit
  error, and that correction is not possible.