COMPUTER ORGANISATION

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COMPUTER ORGANISATION

• Sri.C.R. Rajagopal
• Assistant Professor,
• Vivekananda Institute of Technology,
• Bangalore, INDIA

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Input/output organization
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Objectives

• In this session, you will learn
• Interrupt Hardware
• Enabling and Disabling Interrupts
• Handling Multiple Interrupts
• Controlling Device Requests
• Exceptions
• Introduction to DMA

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Ways of Interrupts

• By external signal
• By special instruction in the program
• By occurrence of some condition

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Interrupt Hardware

• Single level interrupts
• Multi level Interrupts

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Design Issues

• How do you identify the module issuing the
  interrupt?
• How do you deal with multiple interrupts?
• i.e. an interrupt handler being interrupted

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Identifying Interrupting Module

• Different line for each module
• PC
• Limits number of devices
• Software poll
• CPU asks each module in turn
• Slow

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Handling Multiple Interrupts

• Vectored Interrupts
• Fixed Vector address
• Programmable Vector Address
• Interrupt Nesting
• Interrupt Priority
• Daisy chain
• Arrangement of Priority groups

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Interrupt Nesting
Processor
Device p
Device 1
Device 2
Priority arbitration circuit
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Identifying Interrupting Module

• Daisy Chain or Hardware poll
• Interrupt Acknowledge sent down a chain
• Module responsible places vector on bus
• CPU uses vector to identify handler routine
• Bus Master
• Module must claim the bus before it can raise
  interrupt
• e.g. PCI SCSI

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Multiple Interrupts

• Each interrupt line has a priority
• Higher priority lines can interrupt lower
  priority lines
• In bus mastering only current master can
  interrupt

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Daisy Chain

INTR
Processor
Device 1
Device 2
Device n
INTA
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Priority Groups
INTR1
INTA1
INTRn
INTAn
Priority orbitration circuit
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Example - PC Bus

• 80x86 has one interrupt line
• 8086 based systems use one 8259A interrupt
  controller
• 8259A has 8 interrupt lines

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Sequence of Events

• 8259A accepts interrupts
• 8259A determines priority
• 8259A signals 8086 (raises INTR line)
• CPU Acknowledges
• 8259A puts correct vector on data bus
• CPU processes interrupt

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PC Interrupt Layout
IRQ0
IRQ1
IRQ2
IRQ3
INTR
IRQ4
IRQ5
IRQ6
IRQ7
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Exceptions
Debugger

• Interrupts caused by an event
• Traps
• Faults
• Aborts

• Helps Programmer to find the errors
• Trace
• Break points

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Direct Memory Access

• Interrupt driven and programmed I/O require
  active CPU intervention
• Transfer rate is limited
• CPU is tied up
• DMA is the answer

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DMA Function

• Additional Module (hardware) on bus
• DMA controller takes over from CPU for I/O

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DMA Operation

• CPU tells DMA controller-
• Read/Write
• Device address
• Starting address of memory block for data
• Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when finished

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Registers in DMA
Status and Control
IRQ
IE
R/W
Done
0
1
30
31
Starting Address
Word Count
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DMA Transfer Cycle Stealing

• DMA controller takes over bus for a cycle
• Transfer of one word of data
• Not an interrupt
• CPU does not switch context
• CPU suspended just before it accesses bus
• i.e. before an operand or data fetch or a data
  write
• Slows down CPU but not as much as CPU doing
  transfer

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DMA Configurations (1)
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DMA Configurations (1)

• Single Bus, Detached DMA controller
• Each transfer uses bus twice
• I/O to DMA then DMA to memory
• CPU is suspended twice

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DMA Configurations (2)
DMA Controller
Main Memory
CPU
I/O Device
I/O Device
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DMA Configurations (2)

• Single Bus, Integrated DMA controller
• Controller may support gt1 device
• Each transfer uses bus once
• DMA to memory
• CPU is suspended once

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DMA Configurations (3)
DMA Controller
Main Memory
CPU
I/O Device
I/O Device
I/O Device
I/O Device
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DMA Configurations (3)

• Separate I/O Bus
• Bus supports all DMA enabled devices
• Each transfer uses bus once
• DMA to memory
• CPU is suspended once

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Thank you