HDR Gate Level Presentation

1
HDR- Gate Level Presentation

• Team M1
• Emeka Ezekwe (M11)
• Chris Thayer (M12)
• Shabnam Aggarwal (M13)
• Charles Fan (M14)

Team M1 Manager Matthew Russo
2
Status

• Complete
• Specification definition
• Block Diagram
• C Implementation
• Verilog
• Schematic (40 complete)
• Incomplete
• Layout
• Testing

3
HDR in the G80 GPU

• Our decoder is designed to interface between
  specially encoded textures stored on the GPUs
  memory and one of the GPUs texture caches that
  feed into the shader processor.
• Each ROP on nVidias g80 is capable of processing
  4 pixels per clock cycle. We plan for our
  hardware to decode the texture information for 4
  pixels during each clock cycle.
• This decoder will allow smaller textures to be
  stored in the GPUs memory, which will allow
  graphics cards to provide the same functions with
  less memory.
• Ultimately, this decoder can provide savings in
  cost, power consumption, heat dissipation, and
  size in current graphics cards.

4
HDR in the Real World
HDR
http//www.nvidia.com/object/IO_37100.html
5
Design Decisions

• Integer Multiplication has been decided upon
• Wallace tree with booth encoding
• Integer- Floating Point
• ROM is NOT the way. It is slower, bigger, and
  unnecessary. We decided to go with a
  combinational implementation for the I-FP.

6
Integer Multiplier
7
7
Modified Booth Encoder
7
Partial Products
40
Wallace Tree
14
14
Out
14 bit Addition
7
Integer to Floating Point
7
3
1-drag
1
gtgt1
encoder
11
7
6
7
ltlt1
ltlt
5b11111
I-
5
3
21 Mux
5
5b10001
3
OR
8
Block Diagram
8
Reg
Compute 1 pixel
Reg
16
Serialize output
7
Reg
Find G
Compute 1 pixel
Int to FP
Reg
16
Serialize output
7
Reg
4
Compute 1 pixel
Reg
Reg
16
Serialize output
4
Reg
4
Reg
Compute 1 pixel
Reg
16
Serialize output
4
Reg
9
Updated Transistor count
10
Block Area Estimates
11
Initial Floorplan
4
16
Reg
Reg
Compute 1 pixel
Compute 1 pixel
Serial output
4
Reg
Reg
7
16
Reg
Serial output
8
Find G
Int to FP
Reg
Reg
16
Serial output
7
Reg
Compute 1 pixel
Compute 1 pixel
Reg
4
Reg
16
Serial output
4
Reg
12
Revised Floor Plan
F I N D G
7
Int-FP
7
11
11
11
11
11
11
7
R FP- Mult
R FP- Mult
G FP- Mult
G FP- Mult
B FP- Mult
B FP- Mult
Serial Out
Serial Out
11
11
11
11
11
11
11
11
11
Reg
11
11
11
Reg
7
516
11
11
516
Reg
gtgt
Int ()
Reg
gtgt
Int ()
4
4
Reg
3
5
3
5
8
Reg
Reg
Reg
3
5
7
3
5
16
11
Reg
11
11
Reg
gtgt
Int ()
Reg
gtgt
Int ()
4
4
11
11
11
11
11
11
R FP- Mult
R FP- Mult
G FP- Mult
G FP- Mult
B FP- Mult
B FP- Mult
Serial Out
Serial Out
11
11
11
F I N D G
11
11
11
11
11
11
11
11
11
7
Int-FP
7
7
13
Problems and Questions

• Pipelining
• We are planning on inputting a 28 bit register in
  the Integer Multiplier. More work needs to be
  done in this area and will be completed by next
  week.
• For this reason, our critical path cannot
  currently be determined.