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1
Instruction encoding

• Weve already seen some important aspects of
  processor design.
• A datapath contains an ALU, registers and memory.
• Programmers and compilers use instruction sets to
  issue commands.
• Now lets complete our processor with a control
  unit that converts assembly language instructions
  into datapath signals.
• Today well see how control units fit into the
  big picture, and how assembly instructions can be
  represented in a binary format.

2
Block diagram of a processor

• The control unit connects programs with the
  datapath.
• It converts program instructions into control
  words for the datapath, including signals WR, DA,
  AA, BA, MB, FS, MW, MD.
• It executes program instructions in the correct
  sequence.
• It generates the constant input for the
  datapath.
• The datapath also sends information back to the
  control unit. For instance, the ALU status bits
  V, C, N, Z can be inspected by branch
  instructions to alter a programs control flow.

Program
Control signals

Control Unit
Datapath
Status signals
3
A specific instruction set

• The first thing we must do is agree upon an
  instruction set.
• For our example CPU lets stick with the
  three-address, register-to-register instruction
  set architecture introduced in the last lecture.
• Data manipulation instructions have one
  destination and up to two sources, which must be
  either registers or constants.
• We include dedicated load and store instructions
  to transfer data to and from memory.
• Later, well learn about different kinds of
  instruction sets.

4
From assembly to machine language

• Next, we must define a machine language, or a
  binary representation of the assembly
  instructions that our processor supports.
• Our CPU includes three types of instructions,
  which have different operands and will need
  different representations.
• Register format instructions require two source
  registers.
• Immediate format instructions have one source
  register and one constant operand.
• Jump and branch format instructions need one
  source register and one constant address.
• Even though there are three different instruction
  formats, it is best to make their binary
  representations as similar as possible.
• This will make the control unit hardware simpler.
• Well start by making all of our instructions 16
  bits long.

5
Register format

• An instruction involving registers only is
  encoded in this format
• An example register-format instruction
• ADD R1, R2, R3
• Our binary representation for these instructions
  will include
• A 7-bit opcode field, specifying the operation
  (e.g., ADD).
• A 3-bit destination register, DR.
• Two 3-bit source registers, SA and SB.

6
Immediate format

• An example immediate-format instruction
• ADD R1, R2, 3
• Immediate-format instructions will consist of
• A 7-bit instruction opcode.
• A 3-bit destination register, DR.
• A 3-bit source register, SA.
• A 3-bit constant operand, OP.

7
PC-relative jumps and branches

• We will use PC-relative addressing for jumps and
  branches, where the operand specifies the number
  of addresses to jump or branch from the current
  instruction.
• We can assume each instruction occupies one word
  of memory.
• The operand is a signed number.
• Its possible to jump or branch either forwards
  or backwards.
• Backward jumps are often used to implement loops
  see some of the examples from last week.

8
Jump and branch format

• Two example jump and branch instructions
• BZ R3, -24
• JMP 18
• Jump and branch format instructions include
• A 7-bit instruction opcode.
• A 3-bit source register SA for branch conditions.
• A 6-bit address field, AD, for storing jump or
  branch offsets.
• Our branch instructions support only one source
  register. Other types of branches can be
  simulated from these basic ones.

9
The address field AD

• AD is treated as a six-bit signed number, so you
  can branch up to 31 addresses forward (25-1), or
  up to 32 addresses backward (-25).
• The address field is split into two parts for
  uniformity, so the SA field occupies the same
  position in all three instruction formats.

10
Instruction format uniformity

• Notice the similarities between the different
  instruction formats.
• The Opcode field always appears in the same
  position (bits 15-9).
• DR is in the same place for register and
  immediate instructions.
• The SA field also appears in the same position,
  even though this forced us to split AD into two
  parts for jumps and branches.
• Tomorrow well see how this leads to a simpler
  control unit.

11
Instruction formats and the datapath

• The instruction format and datapath are
  inter-related.
• Since register addresses (DR, SA and SB) are
  three bits each, this instruction set can only
  support eight registers.
• The constant operand (OP) is also three bits
  long. Its value will have to be sign-extended if
  the ALU supports wider inputs and outputs.
• Conversely, supporting more registers or larger
  constants would require us to increase the length
  of our machine language instructions.

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Organizing our instructions

• How can we select binary opcodes for each
  possible operation?
• In general, similar instructions should have
  similar opcodes. Again, this will lead to simpler
  control unit hardware.
• We can divide our instructions into eight
  different categories, each of which require
  similar datapath control signals.
• To show the similarities within categories, well
  look at register-based ALU operations and memory
  write operations in detail.

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Register format ALU operations

• ADD R1, R2, R3
• All register format ALU operations need the same
  values for the following control signals
• MB 0, because all operands come from the
  register file.
• MD 0 and WR 1, to save the ALU result back
  into a register.
• MW 0 since RAM is not modified.

WR 1
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Memory write operations

• ST (R0), R1
• All memory write operations need the same values
  for the following control signals
• MB 0, because the data to write comes from the
  register file.
• MD X and WR 0, since none of the registers
  are changed.
• MW 1, to update RAM.

WR 0
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Selecting opcodes

• Instructions in each of these categories are
  similar, so it would be convenient if those
  instructions had similar opcodes.
• Well assign opcodes so that all instructions in
  the same category will have the same first three
  opcode bits (bits 15-13 of the instruction).
• .

16
ALU and shift instructions

• What about the rest of the opcode bits?
• For ALU and shift operations, lets fill in bits
  12-9 of the opcode with FS3-FS0 of the five-bit
  ALU function select code.
• For example, a register-based XOR instruction
  would have the opcode 0001100.
• The first three bits 000 indicate a
  register-based ALU instruction.
• 1100 denotes the ALU XOR function.
• An immediate shift left instruction would have
  the opcode 1011000.
• 101 indicates an immediate shift.
• 1000 denotes a shift left.

17
Branch instructions

• Well implement branch instructions for the eight
  different conditions shown here.
• Bits 11-9 of the opcode field will indicate the
  type of branch. (We only need three bits to
  select one of eight branches, so opcode bit 12
  wont be needed.)
• For example, the branch if zero instruction BZ
  would have the opcode 110x011.
• The first three bits 110 indicate a branch.
• 011 specifies branch if zero.

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Sample opcodes

• Here are some more examples of instructions and
  their corresponding opcodes in our instruction
  set.
• Several opcodes have unused bits.
• We only need three bits to distinguish eight
  types of branches.
• There is only one kind of jump and one kind of
  load instruction.
• These unused opcodes allow for future expansion
  of the instruction set. For instance, we might
  add new instructions or new addressing modes.

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Sample instructions

• Here are complete translations of the
  instructions.
• The meaning of bits 8-0 depends on the
  instruction format.
• The colors are not supposed to blind you, but to
  help you distinguish between destination, source,
  constant and address fields.

20
Where does the program go?

• Well use a Harvard architecture, which includes
  two memory units.
• An instruction memory holds the program.
• A separate data memory is used for computations.
• The advantage is that we can read an instruction
  and load or store data in the same clock cycle.
• For simplicity, our diagrams do not show any WR
  or DATA inputs to the instruction memory.
• Caches in modern CPUs often feature a Harvard
  architecture like this.
• However, there is usually a single main memory
  that holds both program instructions and data, in
  a Von Neumann architecture.

21
Program counter

• A program counter or PC addresses the instruction
  memory, to keep track of the instruction
  currently being executed.
• On each clock cycle, the counter does one of two
  things.
• If Load 0, the PC increments, so the next
  instruction in memory will be executed.
• If Load 1, the PC is updated with Data, which
  represents some address specified in a jump or
  branch instruction.

Data
Load
PC
ADRS Instruction RAM OUT
22
Instruction decoder

• The instruction decoder is a combinational
  circuit that takes a machine language instruction
  and produces the matching control signals for the
  datapath.
• These signals tell the datapath which registers
  or memory locations to access, and what ALU
  operations to perform.

(to the datapath)
23
Jumps and branches

• Finally, the branch control unit decides what the
  PCs next value should be.
• For jumps, the PC should be loaded with the
  target address specified in the instruction.
• For branch instructions, the PC should be loaded
  with the target address only if the corresponding
  status bit is true.
• For all other instructions, the PC should just
  increment.

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Thats it!

• This is the basic control unit. On each clock
  cycle
• 1. An instruction is read from the instruction
  memory.
• 2. The instruction decoder generates the matching
  datapath control word.
• 3. Datapath registers are read and sent to the
  ALU or the data memory.
• 4. ALU or RAM outputs are written back to the
  register file.
• 5. The PC is incremented, or reloaded for
  branches and jumps.

25
The whole processor
Control Unit
Datapath
26
Summary

• Today we defined a binary machine language for
  the instruction set from yesterday.
• Different instructions have different operands
  and formats, but keeping the formats uniform will
  help simplify our hardware.
• We also try to assign similar opcodes to
  similar instructions.
• The instruction encodings and datapath are
  closely related. For example, our opcodes include
  ALU selection codes, and the number of available
  registers is limited by the size of each
  instruction.
• This is just one example of how to define a
  machine language.
• We also saw
• Where the instructions come from (another RAM)
  and
• What components must the control unit have
• Instruction decoder,
• Program Counter (PC) and
• Branch control Unit
• Next, well show how to build a control unit
  corresponding to our datapath and instruction
  set. This will complete our processor!

27
Next Implementing the instruction decoder and
the Branch Unit

• The first thing well look at is how to build the
  instruction decoder.
• The instruction decoders input is a 16-bit
  binary instruction I that comes from the
  instruction memory.
• The decoders output is a control word for the
  datapath. This includes
• WR, DA, AA, BA, and MD signals to control the
  register file.
• FS for the ALU operation.
• MW for the data memory write enable.
• MB for selecting the second operand.
• Well see how these signals are generated for
  each of the three instruction formats.