JSBC Status

1
JSBC Status

• Wei-Ping Yang -CSIST
• Mar.28Mar.30, 2006

2
The Reasons Cause JSBC Failed

• Some signal designs of the FM V1 JSBC are
  marginal. The signal timing and quality may
  varied with the production process and the
  components soldered on the board.
• PPC750 core voltage (VDD) must keep in a steady
  level
• CLK traces need to keep in some specified timing
  relationships
• Series termination of high speed signals must
  match the impedance of PCB track
• JSBC adopted the IBM EVM design but some
  parameters need to be adjusted.
• Some of the layout and placement did not follow
  the layout rules from IBM.

3
What have been found in JSBC FM V1

• PPC750 core voltage (VDD)
• The VDD copper area is not enough, the path from
  regulator to PPC750 was blocked by some via holes
• The capacitance of decoupling capacitors is too
  small
• The placement of decoupling capacitors is not
  good
• PLL CLK routing and series resistors
• CLK routing is not optimized
• Resistance of series resistor not mach to the
  impedance of clock track
• One unnecessary 1ns delay from PPL to PPC750
• SDRAM signals routing and series resistors
• SDRAM clock signal quality is not good
• Address signal quality is not good
• Schematics error
• Wrong Series resistor for PLL feedback signal

4
JSBC FM V1 Rework

• From MIT/CERN testing result, the JSBC FM V1 can
  pass the full functional test after the following
  reworks
• Add R18 on PPC750 CLK path (this effectively
  removes 1ns delay on PPC750 clock)
• Add 220uF and 0.1uF capacitors between VDD pin
  and Ground pin of Sharp regulator
• Remove PPC750 AVdd connection (not necessary for
  current version PPC750 chip)
• Change SDRAM CLOCK series resistors from 61.9 Ohm
  to 24 Ohm
• Change the split resistor values to adjust PPC750
  VDD level
• For the reliability consideration, we decided to
  re-make the JSBC, and the new version will be
  JSBC FM V2.

5
JSBC FM V2

• JSBC FM V2 includes the following modifications
• Change PCB stack to make symmetrically board
  cross section
• PPC750 VDD power
• Add more large capacitance decoupling capacitors
  for regulators
• Enlarge VDD copper area
• Change the placement of decoupling capacitors
• Change the resistance of split resistors to make
  the output voltage near 2.1V
• CLK signals
• Revise the tracks of PPC750 clock and CPC700
  clock (make them shorter)
• Remove PPC750 clock 1ns delay circuit
• Change the pin assignment of PLL chips output to
  provide SDRAM CLK
• Move SDRAM CLK track to layer5 (shield with
  Ground)
• Revise the tracks of PCI clock (make them
  shorter)
• SDRAM Address line
• Change the routing method between SDRAM chips and
  FPGA
• Two Chassis ground planes become Ground planes
• Thermal holes under components are connected to
  ground plane
• Revise the escape patterns for BGA chips
• Enlarge the thermal conducted area of regulators

6
JSBC FM V2 PCB Stack
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PPC750 VDD (Core Voltage) Plane
FM V1 VDD plane
FM V2 VDD plane
8
PLL CLK Layout Routing
9
JSBC FM F6 Schedule