Reconfigurable Computing: A Survey of Systems and Software

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Reconfigurable Computing A Survey of Systems
and Software

• Katherine Compton, Northwestern University,
  andScott Hauck, University of Washington
• Presented by Yi-Gang Tai

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Content

• Introduction
• Technology
• Hardware
• Software
• Run-time reconfiguration (RTR)
• Conclusion

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Introduction
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Conventional Computing

• Hardwired technology ASIC or board-level
  solution
• Fast and efficient
• Expensive to redesign/refabricate
• Software-programmed microprocessors
• Flexible
• Performance may suffer

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Reconfigurable Computing

• To fill the gap between hardware and software
• Major technology field-programmable gate arrays
  (FPGAs)
• Programmable computational elements
• Programmable routing resources
• Digital circuit can be configured to H/W

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Reconfigurable Systems

• Typically formed with a combination of
  reconfigurable logic and a general-purpose
  microprocesor
• Computational cores mapped to reconfigurable
  hardware
• The processor performs operations not efficient
  in reconfigurable logic

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Compilation and RTR

• Compilation environments
• To assist programmers in mapping algorithms to
  H/W
• Run-time reconfiguration
• Device capacity a concern an entire program may
  not fit into the device
• Reconfigure during program execution

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Technology
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Hardware Programmability

• Customizing H/W using physical configuration
  points
• SRAM-programmable
• SRAM bits connected to the configuration points
• Programming SRAM bits configures the FPGA

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Configuring Routing

• Programming bit connecting to SRAM and
  functioning as a switch
• A device could have millions of routing points

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Controlling Multiplexers

• To choose between output of different logic
  resources
• For example, to select output from a stateholding
  D flip-flop (DFF)

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Configuring Computational Unit

• Controlling ALU
• Configuring lookup table (LUT)
• LUTs are basically small memories
• A 3-input LUT

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Hardware
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Reconfigurable Computing Systems

• Frequently coupled with a general-purpose
  processor
• Controlling the reconfigurable logic
• Executing program code not efficient in
  reconfigurable logic
• Two phases of run-time operation
• Configuration
• Execution

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Coupling

• Closely coupled and loosely coupled
• Tradeoff between benefits and drawbacks

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Typical FPGA

• LUT-based Logic blocks
• Island-style routing resources
• Most current FPGAs use less than 10 for logic
  blocks

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A Basic Logic Block
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Logic Block Granularity

• FPGAs based on a set of computation structures
  repeated to form an array
• Logic blocks vary in complexity
• From fine-grained to coarse-grained
• Three input LUT-based
• 4-bit ALU
• Word-width processing elements
• Most current FPGAs are medium-grained,
  heterogeneous arrays
• Use configurable multiplier, memory, etc.

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A Generic Island-style Routing Architecture
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Segmented and Hierarchical Routing Structures
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Software
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Design Flows
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Issues on Software

• Hardware/software partitioning
• Circuit specification
• Structural
• Behavioral
• Circuit libraries
• Circuit Generators
• Parallelization
• Simulation

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Run-time Reconfiguration (RTR)
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Run-time Reconfiguration

• Configurations are too many or too complex to be
  loaded simultaneously
• The concept of virtual hardware similar to
  virtual memory

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Reconfigurable Models
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Pipeline Reconfigurable
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Fast Configuration

• Configuration of entire logic takes hundreds of
  milliseconds
• To reduce the configuration overhead
• Configuration prefetching
• Configuration compression
• Relocation and defragmentation
• Configuration caching

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Conclusion
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Conclusion

• Reconfigurable computing is becoming an important
  research area
• It combines benefits from both S/W and ASIC
  implementations
• Computationally intense portions of an
  application can be put onto the reconfigurable
  H/W to increase performance