Digital Electronics

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Digital Electronics Electronics Technology
Landon Johnson
Counters
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Counter Competencies
29. Given the schematic diagram of a counter
circuit, the student will determine if this
counter is synchronous or asynchronous.
30. Given a schematic of an asynchronous counter,
the student will identify the LSB flip-flop.
31. Given a schematic of a synchronous counter,
the student will identify the LSB flip-flop.
32. Given the schematic of a counter and the
value currently on the counter, the student will
determine the new counter value if an instructor
specified number of pulses are applied to the
counter
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Counter Competencies
33. Given a modulus number from 16 to 32, the
student will draw a schematic of flip-flops and
NAND gates that will count this modulus starting
with zero.
34. Given the schematic diagram of a synchronous
counter circuit, the student will determine the
modulus of the counter.
35. Given the schematic diagram of a synchronous
counter circuit, the student will determine the
counting sequence and list the sequence in
decimal.
36. Given the schematic diagram of a counter and
the clock input frequency, the student will
determine the output frequency of the counter.
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COUNTER UNIT

• Asynchronous up and down counters
• Asynchronous modulus counters
• Seven segment displays/ BCD coding
• Synchronous Counters
• Pre-settable Counters
• Ring Counters

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COUNTERS CHARACTERISTICS
1. MODULUS- number of counts in one cycle
2. Up or down count
3. Asynchronous or synchronous operation
4. Free running or self stopping
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ASYNCHRONOUS COUNTERS

• Only LSB flip-flop controlled by the clock input
• Also known as a RIPPLE COUNTER
• Two or more T flip-flops interconnected, output
  
• of each flip-flop connected to clock input of
  the next.
• Modulus- number of stable states in each
  flip-flop cycle
• Modulus N number of flip-flops
• Highest number in count

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BUILD A 4 BIT RIPPLE COUNTER
1. 4 JK flip-flops in toggle mode- all JK inputs
tied high
2. Q outputs connected to clock input of
following flip-flop
3. FF A LSB (one with clock input) toggles
when input clock toggles from high to low FF
D MSB
4. FF B, C, D do not toggle till receive NGT from
proceeding FF
5. Direction of count can be reversed by
complementing each FFs output or complementing
each FFs input
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TEST
1. What is the term for the number of counts in
one counter cycle?
Modulus of the counter
2. How is the modulus determined?
3. Since only the first flip-flop of a ripple
counter is controlled by a clock, the
counter is ____________________?
Asynchronous
4. What is the mod number of a counter containing
5 flip-flops?
32
5. What is the highest count of a four bit
counter?
31
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PROGRAMMING A RIPPLE COUNTER

• Counters may be made to recycle after any desired
  count by using a gate to reset the
  counter.

CONVERT MOD 8 TO MOD6
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HOW TO BUILD A COUNTER TO GO FROM ZERO TO MOD
NUMBER X
2. Connect a NAND gate output to asynchronous
clears of all FFs
3. Determine which FFs will be high at count
X Connect the Q outputs of these FFs to NAND
gate inputs
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BUILD A COUNTER THAT COUNTS FROM ZERO TO NINE
(XMOD 10)
2. Connect a NAND gate to asynchronous clears of
all FFs
3. Determine which FFs will be high at count
X Connect the Q outputs of these FFs to NAND
gate inputs
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SELF-STOPPING COUNTER

• Counters may be made to stop counting after any
  desired count by using a gate to inhibit the
  clock.

• Stop at desired count

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PROGRAMMING COUNTERS USING JK INPUTS

• Counters can be controlled using the JK inputs

• Low on JK of 1st FF will cause it to stop
  toggling on any count

• High or low at JK inputs forces counter to skip
  states

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ASYNCHRONOUS DOWN COUNTER

• Direction of count can be reversed by
• (a) complementing each FFs output or
• (b) complementing each FFs input

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COUNTER PROBLEM
1. What is the value of the last usable state
before the NAND gate resets the circuitry?
2. What value does the NAND gate reset the value
to?
3. What is the modulus of this counter?
4. If count starts at decimal 11 and receives
seven clock pulses, what is the new value on the
counter?
5. What is the unstable state of the counter?
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COUNTER PROBLEM
1. What is the value of the unstable state, in
decimal?
2. At what value does the NAND gate set the
counter to?
3. If QA1, QB1, and QC0, and 5 clock pulses
are applied QC QB QA
4. What is the modulus of this counter?
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IC ASYNCHRONOUS COUNTERS
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7493 AS A MOD-16 COUNTER
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TEST
Build a MOD 10 counter with a 7493
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BCD COUNTER

• Binary counter that counts from 0000 to 1001
  before it recycles (MOD-10).

• Widespread applications where pulses or events
  are to be counted and the results displayed on a
  decimal numerical read-out.

• Also used for dividing a pulse frequency exactly
  by 10.

Cascading BCD counters to count and display from
000 to 999.
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MOD-60 COUNTER
Two 7493s can be combined to produce a MOD-60
Counter
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DIGITAL CLOCK
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COUNTERS
ASYNCHRONOUS
SYNCHRONOUS
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SYNCHRONOUS COUNTERS

• Two or more FFs connected as T FFs.

• All FFs in the counter are clocked at the same
  time.

• Advantage over the ripple counter is speed and
  accuracy but more complex.

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• A NAND control gate is used to clear the counter
  before the full count.

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SYNCHRONOUS COUNTERS
UP/DOWN
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PRESETTABLE COUNTERS
Can be preset to any desired count. To operate
1. Apply desired count to parallel data inputs
P2, P1, P0.
2. Apply a low pulse to the parallel load input
PL.
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COUNTER TYPES
Asynchronous Counter (a.k.a. Ripple or Serial
Counter) each FF is triggered one
at a time with output of one FF serving as clock
input of next FF in the chain.
Synchronous Counter (a.k.a. Parallel Counter)
all the FFs in the counter are clocked at the
same time.
Up Counter counter counts from zero to a maximum
count.
Down Counter counter counts from a maximum count
down to zero.
BCD Counter counter counts from 0000 to 1001
before it recycles.
Pre-settable Counter counter that can be preset
to any starting count either synchronously or
asynchronously
Ring Counter shift register in which the output
of the last FF is connected back to the input of
the first FF.
Johnson Counter shift register in which the
inverted output of the last FF is connected to
the input of the first FF.
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74193 COUNTER MOD-16 PRESETTABLE UP/DOWN COUNTER
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(No Transcript)
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RING COUNTER
Shift register counter with feedback from Q of
last FF back to first FF input
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JOHNSON COUNTER
Shift register in which the inverted output of
the last FF is fed back to the input of the first
FF.
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Lab 18.
A PROGRAMMABLE COUNTER
Design a four-bit counter controlled by two
control lines X and Y that behaves according to
the truth table.
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Lab 18.
A PROGRAMMABLE COUNTER
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RIPPLE COUNTER
Binary Output
Clock Input
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
Pulse 1
Pulse 2
Pulse 3
Pulse 4
Pulse 5
Pulse 6
Pulse 7
Pulse 8
On the next clock pulse (8) all FFs will toggle
because each will receive a H-to-L pulse- one
after another. Watch the count ripple thru the
counter.
This 4-bit counter has 16 states and will count
from binary 0000 through 1111 and then reset back
to 0000. The counter has a modulus of 16.
All J-K flip-flops in the TOGGLE MODE
PS and CLR input are INACTIVE
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RIPPLE COUNTER WITH WAVEFORMS
Binary Output
Clock Input
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
Pulse 1
Pulse 2
Pulse 3
Pulse 4
Pulse 5
FFs triggered on H-to-L pulse. CLK
toggles 1s FF. 1s FF toggles 2s FF. 2s FF
toggles 4s FF.
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DECADE COUNTER
Initial count at 0111
Binary Output
Clock Input
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
Pulse 1
Pulse 2
Pulse 3
Pulse 4
Pulse 5
Pulse 6
Pulse 7
Pulse 8
All J K inputs 1
All PR inputs 1
To change mod-16 counter to decade counter Reset
count to 0000 after 1001 (9) count. When count
hits 1010 reset to 0000. See added 2-input NAND
gate that clears all JK FFs to 0 when count hits
1010.
Count is at 1001. Next clock pulse will increment
counter for a short time to 1010 which will
activate the NAND gate and reset the counter to
0000.
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DOWN COUNTER
Initial count set at binary 111
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
Pulse 4
Pulse 2
Pulse 1
Pulse 3
Pulse 5
Changes from Ripple Up Counter are wiring from Q
outputs (instead of Q outputs) to the CLK input
of the next FF.
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SELF-STOPPING DOWN COUNTER
Watch count on Pulse 8.
The count remained at binary 000.
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
Pulse 2
Pulse 3
Pulse 4
Pulse 1
Pulse 5
Pulse 6
Pulse 8
Pulse 7
This is a 3-bit down counter. The 1s FF is in
TOGGLE mode when counting (J K 1). The 1s FF
switches to HOLD mode when the J and K inputs are
forced LOW by the OR gate when the count
decrements to 000. The count stops at 000.
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COUNTER USED FOR FREQUENCY DIVISION
? 4
? 8
? 2
? 16
800 Hz
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USING THE 7493 COUNTER IC

• Counters are available in IC form.
• Either ripple (7493 IC) or synchronous (74192 IC)
  counters are available.

1600 Hz
7493 Counter IC wired as a 4-bit binary
counter
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MAGNITUDE COMPARATOR
A magnitude comparator is a combinational logic
device that compares the value of two binary
numbers and responds with one of three outputs
(AB or AgtB or AltB).
Input binary 0001
Input binary 1111
Input binary 0111
HIGH
HIGH
Input binary 1100
HIGH
Input binary 0110
Input binary 0111
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TROUBLESHOOTING EQUIPMENT

• Logic Probe
• Logic Pulser
• Logic Clip (logic monitor)
• Digital IC Tester
• DMM/Logic Probe
• DMM or VOM
• Dual-trace Oscilloscope
• Logic Analyzer

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SIMPLE TROUBLESHOOTING HINTS

• Feel top of IC to determine if it is hot
• Look for broken connections, signs of excessive
  heat
• Smell for overheating
• Check power source
• Trace path of logic through circuit
• Know the normal operation of the circuit