Flipflops

1
Flip-flops

• Combinational logic circuit

2
Basic Latch

• Both circuit are the same
• The only feedback path is the red line

3
Basic Latch

• Consider Set 0, Reset 0

4
Basic Latch

• Consider S 1, R 0
• As S1, NOR1 output must be 0
• As NOR1 ouput 0 and R 0, NOR2 output must be 1

5
Basic Latch

• Consider S 0, R 1
• As R 1, NOR2 output must be 0

6
Basic Latch

• Consider R 1 and S 1
• As R 1, NOR2 output must be 0
• As S 1, NOR1 output must be 0

7
Level sensitive and edge sensitive

• For a latch and flip-flop (FF), it can be level
  sensitive or edge sensitive
• Level sensitive means the latch / FF will copy
  input D to output Q when Clk 1
• Edge sensitive means that the latch / FF will
  only copy input D to output Q when Clk change
  from 0 -gt 1 (positive edge trigger) / 1 -gt 0
  (negative edge trigger)

8
Level sensitive
9
Edge sensitive
10
Representation of Numbers

• Single bit signal
• signal abc STD_LOGIC (define signal)
• abc IN STD_LOGIC (input port)
• Multibit signal
• signal abc STD_LOGIC_VECTOR(3 downto 0)
• signal abc STD_LOGIC_VECTOR(1 to 3)
• abc IN STD_LOGIC_VECTOR(3 downto 0)
• abc IN STD_LOGIC_VECTOR(1 to 3)

11
Assign value to signal

• Vector signal abc std_logic_vector(2 downto 0)
• abc lt 101 (equivalent to the following)
• abc(2) lt 1
• abc(1) lt 0
• abc(0) lt 1
• Single bit signal abc std_logic
• abc lt 1

12
Alignment of multibit signal

• Signal abc std_logic_vector(3 downto 0)
• abc lt 1010
• abc(3) 1, abc(2) 0, abc(1) 1, abc(0) 0
• Signal abc std_logic_vector(0 to 3)
• abc lt 1010
• abc(0) 1, abc(1) 0, abc(2) 1, abc(3) 0

13
Arithmetic (addition)
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_signed.all ENTITY adder16
IS PORT ( X, Y IN STD_LOGIC_VECTOR(15 DOWNTO
0) S OUT STD_LOGIC_VECTOR(15 DOWNTO 0) )
END adder16 ARCHITECTURE Behavior OF adder16
IS BEGIN S lt X Y END Behavior
14
Arithmetic (addition)
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_arith.all ENTITY adder16
IS PORT ( Cin IN STD_LOGIC X, Y IN
SIGNED(15 DOWNTO 0) S OUT SIGNED(16
DOWNTO 0) Cout, Overflow OUT STD_LOGIC )
END adder16 ARCHITECTURE Behavior OF adder16
IS SIGNAL Sum SIGNED(16 DOWNTO 0)
BEGIN Sum lt ('0' X) Y Cin S lt
Sum(15 DOWNTO 0) Cout lt Sum(16) Overflow
lt Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) END
Behavior
Extend to 17 bits, since signal Sum is 17 bit
Carry out is just the 17th bit of Sum
15
If use STD_LOGIC_VECTOR
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_unsigned.all USE
ieee.std_logic_arith.all ENTITY adder16
IS PORT ( Cin IN STD_LOGIC X, Y IN
STD_LOGIC_VECTOR(15 DOWNTO 0) S OUT
STD_LOGIC_VECTOR(16 DOWNTO 0) Cout, Overflow
OUT STD_LOGIC ) END adder16 ARCHITECTURE
Behavior OF adder16 IS SIGNAL Sum
STD_LOGIC_VECTOR(16 DOWNTO 0) BEGIN Sum lt
("0" X) Y Cin S lt Sum(15 DOWNTO 0)
Cout lt Sum(16) Overflow lt Sum(16) XOR
X(15) XOR Y(15) XOR Sum(15) END Behavior
16
Selected signal assignment

• Allows a signal to be assigned one of several
  values, based on a selection criterion
• Examples can be used to implement multiplexer
• WITH-SELECT statement

17
4-to-1 Multiplexer
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 IN
STD_LOGIC s IN STD_LOGIC_VECTOR(1 DOWNTO
0) f OUT STD_LOGIC ) END mux4to1
ARCHITECTURE Behavior OF mux4to1
IS BEGIN WITH s SELECT f lt w0 WHEN
"00", w1 WHEN "01", w2 WHEN "10", w3
WHEN OTHERS END Behavior
Selection based on value of signal s. For
example, when s is 00, value of w0 will
assigned to f
18
2-to-4 binary decoder
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY dec2to4 IS PORT ( w IN
STD_LOGIC_VECTOR(1 DOWNTO 0) En IN
STD_LOGIC y OUT STD_LOGIC_VECTOR(0 TO 3)
) END dec2to4 ARCHITECTURE Behavior OF
dec2to4 IS SIGNAL Enw STD_LOGIC_VECTOR(2
DOWNTO 0) BEGIN Enw lt En w WITH Enw
SELECT y lt "1000" WHEN "100", "0100" WHEN
"101", "0010" WHEN "110", "0001" WHEN
"111", "0000" WHEN OTHERS END Behavior
Concatenation Enw(2) lt En Enw(1) lt
w(1) Enw(0) lt w(0)
y will be assigned with different values based
on value of Enw
19
PORT-MAP statement
LIBRARY ieee USE ieee.std_logic_1164.all
LIBRARY work USE work.mux4to1_package.all
ENTITY mux16to1 IS PORT ( w IN
STD_LOGIC_VECTOR(0 TO 15) s IN
STD_LOGIC_VECTOR(3 DOWNTO 0) f OUT
STD_LOGIC ) END mux16to1 ARCHITECTURE
Structure OF mux16to1 IS SIGNAL m
STD_LOGIC_VECTOR(0 TO 3) BEGIN Mux1 mux4to1
PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0),
m(0) ) Mux2 mux4to1 PORT MAP ( w(4), w(5),
w(6), w(7), s(1 DOWNTO 0), m(1) ) Mux3
mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1
DOWNTO 0), m(2) ) Mux4 mux4to1 PORT MAP (
w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) )
Mux5 mux4to1 PORT MAP ( m(0), m(1), m(2),
m(3), s(3 DOWNTO 2), f ) END Structure
This is an example of building a 16to1
multiplexer using five 4to1 multiplexer.
Port-Map can be regarded as function call in C
language.
20
PORT-MAP continues
LIBRARY ieee USE ieee.std_logic_1164.all
PACKAGE mux4to1_package IS COMPONENT
mux4to1 PORT ( w0, w1, w2, w3 IN STD_LOGIC
s IN STD_LOGIC_VECTOR(1 DOWNTO 0)
f OUT STD_LOGIC ) END COMPONENT END
mux4to1_package
To use PORT-MAP to build a 16to1 multiplexer
using 4to1 multiplexer, in your working
directory, you should have this file named
mux4to1_package.vhd
21
Conditional Signal assignment

• Similar to the selected signal assignment
• Allows a signal to be set to one of several
  values
• WHEN-ELSE statement

22
2-to-1 multiplexer
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY mux2to1 IS PORT ( w0, w1, s
IN STD_LOGIC f OUT STD_LOGIC ) END
mux2to1 ARCHITECTURE Behavior OF mux2to1
IS BEGIN f lt w0 WHEN s '0' ELSE w1 END
Behavior
w0 will assigned to f when s is 0,
otherwise, w1 assigned to f
23
Priority encoder
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY priority IS PORT ( w IN
STD_LOGIC_VECTOR(3 DOWNTO 0) y OUT
STD_LOGIC_VECTOR(1 DOWNTO 0) z OUT
STD_LOGIC ) END priority ARCHITECTURE
Behavior OF priority IS BEGIN y lt "11" WHEN
w(3) '1' ELSE "10" WHEN w(2) '1'
ELSE "01" WHEN w(1) '1' ELSE "00" z lt
'0' WHEN w "0000" ELSE '1' END Behavior
Different value assigned to y based on
different selection criterion
24
Generate Statement

• Some regular structure of codes could be written
  in a more compact form using a loop
• FOR statement
• It is different from the for-loop statement in
  C language, in here, FOR loop means duplicate

25
16-to-1 multiplexer
LIBRARY ieee USE ieee.std_logic_1164.all USE
work.mux4to1_package.all ENTITY mux16to1
IS PORT ( w IN STD_LOGIC_VECTOR(0 TO 15)
s IN STD_LOGIC_VECTOR(3 DOWNTO 0) f
OUT STD_LOGIC ) END mux16to1
ARCHITECTURE Structure OF mux16to1 IS SIGNAL
m STD_LOGIC_VECTOR(0 TO 3) BEGIN G1 FOR i
IN 0 TO 3 GENERATE Muxes mux4to1 PORT MAP
( w(4i), w(4i1), w(4i2), w(4i3), s(1
DOWNTO 0), m(i) ) END GENERATE Mux5
mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3
DOWNTO 2), f ) END Structure
26
Process Statement

• All VHDL statement executed in concurrent
• Some statement executed in sequential
• These kinds of statements are placed inside a
  process statement
• For example IF-THEN-ELSE statement

27
Priority encoder
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY priority IS PORT ( w IN
STD_LOGIC_VECTOR(3 DOWNTO 0) y OUT
STD_LOGIC_VECTOR(1 DOWNTO 0) z OUT
STD_LOGIC ) END priority ARCHITECTURE
Behavior OF priority IS BEGIN PROCESS ( w
) BEGIN IF w(3) '1' THEN y lt "11"
ELSIF w(2) '1' THEN y lt "10" ELSIF
w(1) '1' THEN y lt "01" ELSE y lt
"00" END IF END PROCESS z lt '0' WHEN
w "0000" ELSE '1' END Behavior
Process will be executed when value of w change
Inside process, statements executed in sequential
Executed in concurrent
Executed in concurrent
28
Case Statement

• Similar to select statement
• Case statement used inside process statement

29
2-to-4 binary decoder
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY dec2to4 IS PORT ( w IN
STD_LOGIC_VECTOR(1 DOWNTO 0) En IN
STD_LOGIC y OUT STD_LOGIC_VECTOR(0 TO 3)
) END dec2to4 ARCHITECTURE Behavior OF
dec2to4 IS BEGIN PROCESS ( w, En ) BEGIN IF
En '1' THEN CASE w IS WHEN "00" gt y lt
"1000" WHEN "01" gt y lt "0100" WHEN
"10" gt y lt "0010" WHEN OTHERS gt y lt
"0001" END CASE ELSE y lt "0000"
END IF END PROCESS END Behavior
Process will be executed when value of w or
En change
y assigned with different value based on value
of w