Quiz 4 Solution

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Quiz 4 Solution
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• Frequency 2.5GHz , CLK 0.4ns
• CPI 0.4, 30 loads and stores,
• L1 hit 0,
• L1-ICACHE 2 miss rate, 32-byte blocks
• L1-DCACHE 5 miss rate, 16-byte blocks
• L2-Cache 10 miss rate, access time15 ns,
  64-byte blocks
• Memory access time 75 ns
• Miss penalty for data between L1 and
  L215ns16/162.5ns17.5ns
• Miss penalty for inst between L1 and L2
  15ns32/162.5ns 20ns
• Miss penalty between L2 and Memory
  75ns64/167.5ns 105ns
• Part a)
• DATA_AMAT L1 hit time L1 data miss rate ( L2
  hit rate(Data in L2 penalty)L2 miss rate (Data
  not in L2 but in memory penalty))
• 00.05(0.9(17.5)0.1(17.5105))1.4
• INST_AMAT L1 hit time L1 inst miss rate ( L2
  hit rate(inst in L2 penalty)L2 miss rate (inst
  not in L2 but in memory penalty))
• 00.02(0.9(20)0.1(20105))0.61

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• Frequency 2.5GHz , CLK 0.4ns
• CPI 0.4, 30 loads and stores,
• L1 hit 0,
• L1-ICACHE 2 miss rate, 32-byte blocks
• L1-DCACHE 5 miss rate, 16-byte blocks
• L2-Cache 10 miss rate, access time15 ns,
  64-byte blocks
• Memory access time 75 ns
• DATA_AMAT
• 00.05(0.9(17.5)0.1(17.5105))1.4
• INST_AMAT
• 00.02(0.9(20)0.1(20105))0.61
• Part b)
• Over-all CPI Ideal CPIimpact of data
  accessesimpact of inst accesses
• 0.4(0.3(AMAT_DATA)1(AMAT_INST))xfrequency
• We need to take frequency into account as this is
  CPI and not execution time.
• 0.4((0.3(1.4)1(0.61))2.5GHZ)2.975

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• Frequency 2.5GHz , CLK 0.4ns
• CPI 0.4, 30 loads and stores,
• L1 hit 0,
• L1-ICACHE 2 miss rate, 32-byte blocks
• L1-DCACHE 5 miss rate, 16-byte blocks
• L2-Cache 10 miss rate, access time15 ns,
  64-byte blocks
• Memory access time 75 ns
• Over-all CPI0.4((0.3(1.4)1(0.61))2.5GHZ)2.975
  
• Part c) Replace 2.5GHZ processor w/ 3.6GHZ.
  Improvement?
• New CPI0.4((0.3(1.4)1(0.61))3.6GHZ)4.1
• execution timeCPIClock period
• Improvementold execution time/new execution time
• (2.975/2.5)/(4.1/3.6)
  1.19/1.131.05
• 5 improvement!

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• Part d)
• 1-Bigger L1, cut missrate to half, L1 hit 1
  cycle 0.4 ns
• DATA_AMAT L1 hit time L1 data miss rate ( L2
  hit rate(Data in L2 penalty)L2 miss rate (Data
  not in L2 but in memory penalty))
• 0.40.025(0.9(17.5)0.1(17.5105))1.1
• INST_AMAT L1 hit time L1 inst miss rate ( L2
  hit rate(inst in L2 penalty)L2 miss rate (inst
  not in L2 but in memory penalty))
• 0.40.01(0.9(20)0.1(20105))0.7
• Over-all CPI Ideal CPIimpact of data
  accessesimpact of inst accesses
• 0.4(0.3(AMAT_DATA)1(AMAT_INST))xfrequency
• 0.4(0.3(1.1)1(0.7))frequency2.975. No
  improvement.

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• Part d)
• 2-Smaller L2, L2 access time 10 , L2 miss
  rate15
• Miss penalty for data between L1 and
  L210ns16/162.5ns12.5ns
• Miss penalty for inst between L1 and L2
  10ns32/162.5ns 15ns
• DATA_AMAT L1 hit time L1 data miss rate ( L2
  hit rate(Data in L2 penalty)L2 miss rate (Data
  not in L2 but in memory penalty))
• 00.05(0.85(12.5)0.15(12.5105))1.41
• INST_AMAT L1 hit time L1 inst miss rate ( L2
  hit rate(inst in L2 penalty)L2 miss rate (inst
  not in L2 but in memory penalty))
• 00.02(0.85(15)0.15(15105))0.61
• Over-all CPI Ideal CPIimpact of data
  accessesimpact of inst accesses
• 0.4(0.3(AMAT_DATA)1(AMAT_INST))xfrequency
• 0.4(0.3(1.41)1(0.61))frequency2.982. lose
  performance.