An instable circuit example

1
An instable circuit example

• Initial Q1 and D0
• Outputs at Q
• T1 Q1
• T2 Q1
• T3 Q1
• stabled

• Assume gate delay is 1ns
• Initial Q1 and D1
• Outputs at Q
• T1 Q0
• T2 Q1
• T3 Q0
• .not stabled

D
Q
2
D-latch

• Two inputs
• the data value to be stored (D)
• the clock signal (C) indicating when to read
  store D
• Two outputs
• the value of the internal state (Q) and it's
  complement
• The input D is allowed to propagate to Q only
  when C1

3
D-latch Behavior Zoomed Out
C
D1
Q
_
Q
D2
D
D
Clock enabled
C
D1
D2
Change in D2 cause Q from 1-gt0, notice the gate
delay
Q
Change in Q cause Q from 0-gt1, notice the gate
delay
Q
4
D flip-flop

• Output changes only on the clock edge