Implementing a PetriNet Specification on FPGA

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Implementing a Petri-Net Specification on FPGA

• By
• Pratibha Sharma
• (2003JVL0014)

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Outline

• Introduction to Petri-Nets
• Why FPGA?
• Why VHDL?
• Schematics for
• a) Place
• b) Transition
• Implementation
• Conclusions

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Petri-nets

• Place Residence of tokens.
• Transition Consumes and produces tokens from and
  to places, when fired.
• Number of tokens produced and consumed equals
  weight of the directed arcs from places to
  transitions.

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Petri-Nets contd
Effective in describing and analysing concurrent
and real-time systems.
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Why FPGA?

• Expensive fabrication techniques not required
  thus reduced cost.
• Prospects to update hardware as easily as
  software.
• Reduced Time to market.
• Higher Integration.
• Increased Performance.
• Improved System Debugging.

Best for small space systems having small life
cycles.
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Why VHDL?

• Standard hardware description language
  independent of implementation.
• Supported by a number of simulation and synthesis
  tools

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Schematic for Place

• T Signals from Preceding Transitions, Sets
  LS
• R Signals form Next Transitions, Resets LS
  when T0
• LS Input to next transitions
• Single token implementation
• One Hot Encoding

OR
AND
OR
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Schematic for Transition

• E External inputs to the system.
• L Signals form the preceding places.
• LE sets TS on negative edge of the clock which
  remains 1 for one clock cycle.

AND
DELAY
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Petri-net modelling
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Transformation

• For more compact design can code Place with
  reduced number of state bits, number of CLB s
  decreases.
• but
• a) Sometimes on dividing use more CLB s.
• b) Verification may become difficult.

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Implementation

• System to be divided into low complexity
  subsystems.
• Strong division for integrating subsystems into
  CLB s with 4-5 inputs.
• CLB s interconnected with buses of limited
  capacity, bring close subsystems with strong
  dependence.
• Minimize number of interconnection between CLB s.

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Implementation contd

• Block (subsystem)
• Using VHDL
• Example

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BLOCK

• One Place and one Transition
• T activates Place, R or transition in the same
  block resets it.
• Transition active when preceding place is active
  and the transition inputs have appropriate values

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Petri-net modelling
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BLOCK contd

• Every block has two outputs LS, the state bit
  for Place, and TS, the Transition bit.
• Single CLB implementation
• Large m, n and p unusual.
• Cases with large m, n and p
• a)Common resource, or
• b)Synchronization points.

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Handling large number of inputs
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Using VHDL

• Block having single place and transition serves
  as component.
• Petri-Nets specification divided into such
  blocks.
• The divided net directly transformed to VHDL code
  connecting these components .

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Example Petri-net
Divide into blocks for its implementation
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Schematic with configurable blocks
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Conclusions

• VHDL description guarantees correct
  representation as long the Petri-net does it.
• Approach optimal for Petri-nets with less inputs
  to Places and Transitions - much faster and
  consumes less FPGA resources than schematic or
  VHDL behavior methodologies.

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THANKS