CSCE 611: Memory Interface Design

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CSCE 611Memory Interface Design

• Instructor Jason D. Bakos

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Introduction

• Goal of the next unit
• Interface your CPU to a memory model
• Design two components that will reconcile the
  interface differences between the CPUs memory
  interface and the models interface
• Use the memory model to perform a comprehensive
  test of all instructions in our instruction set

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Introduction

• Book presented a simplistic memory interface
• Our processor uses a slightly more realistic
  memory interface
• Interface signals
• MemRead(out), MemWrite(out), MemWait(in),
  MemoryAddress(out), MemoryDataOut(out),
  MemoryDataIn(in)
• Byte-addressed
• Reads and writes performed in 32-bit units
• Rising-edge active
• Handshaking bus protocol

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Memory Model

• GOAL
• Add a model of a real memory to the top-level
  design
• Advantages over current method
• More closely matches actual behavior of memory
  and memory interface
• Load the memory model with arbitrary program and
  use it to hold data (perform loads and stores)

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Memory Model

• The memory model is a VHDL behavioral model from
  an FPGA computing card
• The memory model is
• Word addressed
• Different set of interface signals, different bus
  protocol
• It uses a bus arbitration protocol
• Encapsulates the bahavior of the memory and a
  centralized arbiter
• Size 128K x 32
• The goal of this unit is to reconcile these
  differences and use this memory for our processor

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Memory Access Latency

• Basic idea
• Reading or writing a word in memory requires gt 1
  CPU clock cycle
• Why?
• Decoding latency
• Bus protocol management overhead (arbitration)

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Bus Arbitration

• We use a bus for the processor to access the
  memory
• A bus is a shared communication link
• How is the bus reserved by a device that wishes
  it to communicate?
• Single Master
• CPU is master, memory/(all others) is slave (we
  assumed this before)
• Multiple Master
• Requires bus arbitration
• Arbiter may decide who is the bus master
• Arbiter may employ priority

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Bus Arbitration Schemes

• Bus arbitration schemes (control signals shown)

• Daisy chain

• Centralized, parallel

• Distributed by collision detection

• Distributed by self-selection

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Memory Bus

• FPGA card has two FPGAs that may desire to use
  the memory
• Memory bus consists of an address bus (24-bit)
  and two data buses (32-bit)
• Control signals are used by the FPGAs to gain
  access to the bus (become bus master)

Shared bus
Local control
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Memory Read
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Burst Read
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Memory Write
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Burst Write
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Bus Arbitration

• In order to use the memory on the Wild-One card,
  we use centralized bus arbitration
• Control signals
• MemBusReq_n, MemStrobe_n, MemWriteSel_n
• MemBusGrant_n
• Data signals
• MemAddr_OutReg, MemData_OutReg
• MemData_InReg
• A bus controller will reconcile the differences
  between the existing handshaking protocol and
  this protocol
• Uses the MemWait signal to stall the processor
  while arbitration is being performed on behalf of
  the processor

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Alignment

• The next problem we must solve
• MemAddr_OutReg is word aligned
• Byte address bits 1 and 0 (from our CPU) are not
  used
• Must do something about LH and LB which do not
  address the low-order portion of the word
• Solution use little-endian addressing

Half words within word
Bytes within word
Because the processor sign/zero-extends the
low-order portion of the word on a LH, LHU, LB,
LBU, we just need to shift the contents right by
a number of bits specified by the byte offset
(shift amount 8 addr(10))
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Alignment

• Assume word at specified address is 89ABCDEF
• Load word
• addr(10) must be 00 to be aligned on word
  boundary
• do nothing
• Load half word
• addr(10) may be
• 00 (load low-order half of word)
• CPU will sign-extend or zero-extend FFFFCDEF
• 10 (load high-order half of word)
• Alignment unit must SHIFT the word 16 bits to the
  right 000089AB
• then CPU will sign-extend or zero-extend
  FFFF89AB

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Alignment

• Assume word at specified address is 89ABCDEF
• Load byte
• addr(10) may be
• 00 (load lowest-order byte)
• CPU will sign-extend or zero-extend FFFFFFEF
• 01 (load second-to-lowest order byte)
• Alignment unit will shift 8 bits to the right
  0089ABCD
• CPU will sign-extend or zero-extend FFFFFFCD
• 10 (load second-highest order byte)
• Alignment unit will shift 16 bits to the right
  000089AB
• CPU will sign-extend or zero-extend FFFFFFAB
• 11 (load highest-order byte)
• Alignment unit will shift 24 bits to the right
  000089AB
• CPU will sign-extend or zero-extend FFFFFF89

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Store Halfword/Store Byte

• We can only write memory in units of words
• For SH/SB, wed need to pre-fetch the word inside
  which we are storing the half
• A data cache will do this for us, so lets wait
  until Lab 5
• Until then treat SH and SB as SW

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Adding the Memory Model
Memory model from CSELib
Parts you will design Bus controller
Data alignment unit
Your current CPU Design
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Lab 4 (Simpletest Simulation)

• Simpletest is a machine-code program that can be
  loaded into the memory model and executed with
  your CPU
• Tests all instructions from your instruction set
  (except SH, SB)
• Three sections
• Arithmetic/logic/shift/comparison instructions
• Branch/jump section
• Store section
• Due date Tuesday, April 10 500 pm

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Additional Notes

• Pin names on memory model are named from the
  point of view of the CPU (i.e. in, out)
• Word address on the memory model is 24-bits
• Connects to CPUs MemoryAddressOut(25 downto 2)
• Simpletest
• simpletest.s assembly code file
• simpletest.lst listing file from SPIM
• simpletest.bin machine-code file
• Download this file from the webpage and point the
  memorymodel to it