CSCE 611: Designing a Unified Cache

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CSCE 611Designing a Unified Cache

• Instructor Jason D. Bakos

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Caches

• A cache is a memory that stores a subset of the
  main system memory
• It allows for fast access to memory locations
  that are stored in the cache
• Access to memory locations in the cache are
  faster than accesses to main memory
• Implemented with SRAM as opposed to DRAM
• Caches are on-chip
• Caches are smaller than main memory

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Caches

• The cache is part of the memory hierarchy
• CPU memory interface is connected only to the
  cache
• CPU reads/writes to a location in the cache
• Cache hit
• Can be performed in one clock cycle
• CPU reads/writes to a location not in the cache
• Cache miss
• Cache must delay CPU and retrieve the location
  from memory

main memory
cache
CPU
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Caches

• Caches speed up average memory access time using
  two principals
• Temporal locality
• The same memory location tends to be accessed
  multiple times during the execution of a program
• Spatial locality
• Closely addressed memory locations tend to be
  accessed together (i.e. arrays and data
  structures)
• For this reason, the cache is designed as a set
  of cache lines, where each line stores multiple
  consecutive words

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Designing Your Cache

• We will design a simple cache with the following
  attributes
• Direct-mapped
• Each memory address can exist within only one
  possible cache line
• For any memory access, the cache only needs to
  check one cache line to see if the word is in the
  cache
• If not, the cache line is replaced with a new
  cache line that contains the word
• This is a cache miss
• Write-back
• When a word is written to the cache, the cache
  line is marked as dirty
• When a dirty cache line is replaced, the line is
  first written to memory

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Cache Layout

• Here is a 8 line cache, where each line is 4
  words

word is indexed by address(32)
line is indexed by address(64)
tag is address(317)
valid
dirty
tag
word0
word1
word2
word3
line
0
1
2
3
4
5
6
7
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Cache Controller

• Cache hits may be performed combinationally
• Also allow for halfword and byte writes
• The cache controller must
• interface with the memory model
• Use burst reads and writes
• service cache misses
• miss on clean line (replace a cache line, make
  CPU wait)
• miss on dirty line (write line back to memory,
  replace cache line, make CPU wait)

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Cache Controller Operation

• When the CPU performs a memory access
• If corresponding line isnt valid or tag
  mismatches
• Raise wait signal
• Request memory bus from arbiter
• If dirty bit is set, burst write the line to
  memory, else skip
• Burst read the cache line from memory
• Write tag, valid bit, and dirty bit
• Else, if the access is a write, mark dirty bit
  for the corresponding cache line

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Notes

• Design a 1-bit register for valid and dirty bits
• Use 32x1 RAM component in CSELib for tag and
  cache data

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Notes

• 32x1 RAM is 32 individually addressable bits
• Use in parallel to design arbitrary RAM
  structures
• Use hierarchy to manage design size
• 32x8 RAM
• 32x32 RAM
• Tag size should be based on 24-bit addresses from
  MemoryModel
• Design a 32 line, 4 word/line direct-mapped
  write-back cache and use as a unified cache
• Use to run Simpletest
• Due date Friday, April 27
• What to turn in
• Waves from Simpletest simulation
• Cache designs (no generated VHDL)