TransistorTransistor Logic and BiCMOS

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Transistor-Transistor Logic and BiCMOS

• Dr. T.Y. Chang
• NTHU EE
• 2007.12.11_13

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Introduction

• Diode-Transistor Logic
• Basic TTL NAND gate
• Schottky TTL
• BiCMOS
• Text Book D.A. Neamen, Electronic Circuits
  Analysis And Design, 2nd ed. Chapters 17.

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Parameters
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Diode-Transistor Logic
Logic-15V Logic-00.1V
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Example 17.8 _at_p1137

• Find Is and Vs in DTL as shown in Fig. 17.20 with
  ?25.

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Evolution
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Multi-Emitter Cross Section
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TTL Inputs
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TTL
Ex 17.9 Find Is, Vs, and Max. Fanout of Fig.
17.24. ?R0.1, ? 25.

• If No Rc ? Called
• Open-Collector TTL (OC TTL)

• Wired-AND
• Connects outputs of OC TTLs
• and adds an Rc

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TTL with Totem-Pole Output
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TTL Layout
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Fanout
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Modified Totem-Pole TTL
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Tristate Output
0 switch open 1 switch on
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Schottky BJT
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Schottky TTL
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Low-Power Schottky TTL
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Example 17.12 _at_p1154

• Calculate power dissipation in Fig. 17.34 with
  ?25, V?0.7V, VCE(sat)0.4V.

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Advanced Schottky TTL
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BiCMOS

• CMOS
• Low Power
• Slower
• BJT
• Faster
• High Power
• Core CMOS, Interface BJT

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Basic BiCMOS Inverter

• Totem-Pole Configuration (Q1-Q2)
• Turn-off time
• VOHVDD-VBE(ON)
• VOLVBE(ON)

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0
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BiCMOS Inverters
0V or VDD
VBE(ON) or VDD? VBE(ON)
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BiCMOS Inverter I

• Reduce Turn-off time
• bleeder resistors R1 and R2 are added
• VOHVDD-VBE(ON)
• VOLVBE(ON)

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BiCMOS Inverter II

• Reduce Turn-off time
• VOHVDD and VOL0

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BiCMOS NAND2 Gate
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BiCMOS NOR
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Problem (Not HW)

• Implement EABCD in two-level TTL gates.
• Implement a BiCMOS NAND gate.

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Solutions

• EABCD
• ((AB) (CD))