Generating Checking Sequences for a Distributed Test Architecture

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Generating Checking Sequences for a Distributed
Test Architecture

• Hasan Ural
• Craig Williams

• School of Information Technology
• Engineering
• University of Ottawa, Canada

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Outline

• FSM based Testing
• Distributed Test Architectures
• Coordination Problems in Distributed Testing
• Controllability Problem
• Observability Problem
• Proposed Solution
• Summary Directions for Future Research

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FSM based Testing

• Finite State Machine Model
• Objective of Testing
• Fault Models
• State Identification

DS ab
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Local Test Architecture
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Distributed Test Architecture
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Controllability Problem

• Problem Determine when to send input

?U a, ?L b ?U 0, ?L 1
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Controllability Solution

• External coordination message
• exchanges relating to controllability
• Consider
• t2 a/lt0,-gt and t3 b/lt-,1gt
• Global input/output sequence becomes
• a/lt0,-gt lt-CL, CUgt b/lt-,1gt CR 99

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Observability Problem

• Problem Determine whether the observed output
  is generated by the correct transition

?U a, ?L b ?U 0, ?L 1,2
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Observability Solution

• External coordination message
• exchanges relating to observability
• Consider
• t1 a/lt0,1gt and t3 b/lt-,2gt
• Faulty a/lt-,1gt and b/lt0,2gt
• Global input/output sequence becomes
• a/lt0,1gt lt-OU, OLgt b/lt-,2gt CR 99

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Problem

• Given an FSM M, construct a checking sequence
  which
• distinguishes M from any faulty implementation of
  M
• causes no controllability and observability
  problems
• is efficient in terms of both the number external
  coordination message exchanges required and
  overall length of the checking sequence

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Solution

• Assumes reliable reset and existence of DS
• 4 Phases
• Identify potential controllability
  observability problems
• Generate test segments
• Generate a preamble from s1 to si for each state
  si
• Construct concatenate state and transition
  covers

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Controllability Observability

• Identify potential problems
• for every vertex vj
• for every edge entering vertex vj
• for every edge leaving vertex vj
• Sets TC, TO
• TC (t3, t10, lt-CU, CLgt),
• TO (t2, t4, lt-OL, OUgt),

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Test Segments

• Verify each transition tij by a test segment
• test(tij) tij _at_ DS(sj)
• Insert external coordination message exchanges
  relating to controllability and observability in
  each test segment
• Remove triples from TO
• Message exchange for only one occurrence of each
  potential undetectable 1-shift output fault is
  sufficient

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Preambles

• Path from s1 to si for each state si
• Preamble(si) is used
• Once for the identification of si
• Once for the test segment for each transition
  originating at si
• Goals are to minimize
• Observability controllability problems within
  preamble
• Observability controllability problems between
  last transition of preamble and transitions
  starting at si
• Length of preamble

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Preamble costs (1)
?U b, ?L a, c ?U 0, 1, ?L 2, 3
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Preamble costs (2)
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Preamble costs (3)
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Subsequences in state and transition covers

• State cover
• for each state si
• preamble(si) _at_ DS(si)
• Transition cover
• for each transition tij
• preamble(si) _at_ test(tij)
• where test(tij) tij _at_ DS(sj)

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Ordering of subsequences

• Prefix
• elimination
• rfU and rfL
• Ordering

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Summary

• Method for generating checking sequences
• for distributed testing
• Resulting checking sequences have no
  controllability and observability problems
• Performs at least as well as other methods
• For a given FSM DS, a checking sequence that
  does not require ext. coordination message
  exchanges is selected if a nonempty set of such
  sequences exists

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Additional work

• Solution extended for np-FSMs, n gt 2
• Solution extended to the case
• which does not require reliable reset

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Directions for Future Research

• State identification using UIOs, characterizing
  sets, prefixes of distinguishing sequences
• Algorithmic removal of redundant external
  coordination message exchanges relating to
  observability
• k-shift output faults, k ? 2