William Stallings Computer Organization and Architecture 6th Edition

1
William Stallings Computer Organization and
Architecture6th Edition

• Chapter 3
• System Buses

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Program Concept

• Hardwired systems are inflexible
• General purpose hardware can do different tasks,
  given correct control signals
• Instead of re-wiring, supply a new set of control
  signals

Instruction Codes
Instruction interpreter
Customized Hardware
Control Signal
Sequence of arithmetic and logic functions
Data
Results
General-purpose arithmetic and logic functions
Results
Data
Programming in hardware
Programming in software
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What is a program?

• A sequence of steps or instructions is called
  software.
• For each step, an arithmetic or logical operation
  is done
• For each operation, a different set of control
  signals is needed

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Function of Control Unit

• For each operation a unique code is provided
• e.g. ADD, MOVE
• A hardware segment accepts the code and issues
  the control signals
• We have a computer!

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Components

• The Control Unit and the Arithmetic and Logic
  Unit constitute the Central Processing Unit (CPU)
• Data and instructions need to get into the system
  and results out
• Input/output
• Temporary storage of code and results is needed
• Main memory

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Computer ComponentsTop Level View
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Registers in CPU

• PC (Program Counter)
• Holds the address of the instruction to be
  fetched next.
• IR (Instruction Register)
• Stored the fetched instruction.
• MAR (Memory Address Register)
• Specifies the address in memory for the next read
  or write.
• MBR (Memory Buffer Register)
• Contains the data to be written into memory, or
  receives the data from memory.
• I/O AR (I/O Address Register)
• Specifies a particular I/O device.
• I/O BR (I/O Buffer Register)
• Exchange of data between an I/O module and the
  CPU.

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Computer Function

• The basic function performed by a computer is
  execution of a program, which consists of a set
  of instructions stored in memory.

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Instruction Cycle

• Instruction processing consists of two steps
• Fetch fetches instructions from memory
• Execute executes each instruction

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Fetch Cycle

• Program Counter (PC) holds address of next
  instruction to fetch
• Processor fetches instruction from memory
  location pointed by PC
• Increment PC
• Unless told otherwise
• Instruction loaded into Instruction Register (IR)
• Processor interprets instruction and performs
  required actions

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Execute Cycle

• The processor interprets the instruction and
  performs the require action. These actions are
• Processor-memory
• data transfer between CPU and main memory
• Processor-I/O
• Data transfer between CPU and I/O module
• Data processing
• Some arithmetic or logical operation on data
• Control
• Alteration of sequence of operations
• e.g. jump
• Combination of above

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Characteristics of a Hypothetical machine
(a) Instruction Format
(b) Integer Format
Program Counter (PC)address of
instruction Instruction Register (IR)
Instruction being executed Accumulator
(AC)temporary Storage
(c) Internal CPU Opcodes
0001load from memory 0010store AC to
memory 0101add to AC from memory
(d) Partial list of Opcodes
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Example of Program Execution
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Instruction Cycle

• The instruction cycle consists of following
  states
• Instruction address calculation
• Determine the address of the next instruction to
  be executed
• Instruction fetch
• Read instruction from its memory location into
  the processor
• Instruction operation decoding
• Analyze instruction to determine type of
  operation to be performed and operands to be used
• Operand address calculation
• Determine the address of the operand
• Operand fetch
• Fetch the operand from memory or read it in from
  I/O
• Data operation
• Perform the operation indicated in the
  instruction
• Operand store
• Write the result into memory or out to I/O

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Instruction Cycle - State Diagram
ADD B, A AAB
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Interrupts

• Mechanism by which other modules (e.g. I/O) may
  interrupt normal sequence of processing
• Classes of Interrupts
• Program
• e.g. overflow, division by zero
• Timer
• Generated by internal processor timer
• Used in pre-emptive multi-tasking
• I/O
• from I/O controller
• Hardware failure
• e.g. memory parity error

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Program Flow Control
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Transfer of Control via Interrupts
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Interrupt Cycle

• Added to instruction cycle
• Processor checks for interrupt
• Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending
• Suspend execution of current program
• Save context
• Set PC to start address of interrupt handler
  routine
• Process interrupt
• Restore context and continue interrupted program

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Instruction Cycle with Interrupts
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Program TimingShort I/O Wait
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Program TimingLong I/O Wait
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Instruction Cycle (with Interrupts) - State
Diagram
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Multiple Interrupts

• Two approaches to dealing with multiple
  interrupts
• Disable interrupts
• Processor will ignore further interrupts while
  processing one interrupt
• Interrupts remain pending and are checked after
  first interrupt has been processed
• Interrupts handled in sequence as they occur
• Define priorities
• Low priority interrupts can be interrupted by
  higher priority interrupts
• When higher priority interrupt has been
  processed, processor returns to previous interrupt

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Multiple Interrupts - Sequential
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Multiple Interrupts Nested
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Time Sequence of Multiple Interrupts
Interrupt Service Routine, ISR
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Interconnection Structures

• A computer consists of a set of components
• Processor
• Memory
• I/O
• All the units must be connected
• Interconnection structure
• The collection of paths connecting the various
  modules
• Different type of connection for different type
  of unit
• Memory to processor
• Processor to memory
• I/O to processor
• Processor to I/O
• I/O to or from memory

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Computer Modules
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Memory Connection

• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
• Read
• Write
• Timing

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Input/Output Connection(1)

• I/O is functionally similar to memory from
  computers viewpoint
• Read
• write
• Output
• Receive data from computer
• Send data to peripheral
• Input
• Receive data from peripheral
• Send data to computer

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Input/Output Connection(2)

• Receive control signals from computer
• Send control signals to peripherals
• e.g. spin disk
• Receive addresses from computer
• e.g. port number to identify peripheral
• Send interrupt signals (control)

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CPU Connection

• The CPU reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives ( acts on) interrupts

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• The interconnection structure must support the
  following types of transfers
• Memory to processor
• Processor to memory
• I/O to processor
• Processor to I/O
• I/O to/from memory
• DMA

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What is a Bus?

• A communication pathway connecting two or more
  devices
• Shared transmission medium
• Usually broadcast
• Often grouped
• A number of channels in one bus
• e.g. 32 bit data bus is 32 separate single bit
  channels
• Power lines may not be shown

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Buses

• There are a number of possible interconnection
  systems
• Single and multiple BUS structures are most
  common
• Three functional groups
• Data bus
• Address bus
• Control bus

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Bus Interconnection Scheme
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Data Bus

• Carries data
• Remember that there is no difference between
  data and instruction at this level
• Width is a key determinant of performance
• The number of lines determines how many bits can
  be transferred at a time.
• 8, 16, 32, 64 bit

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Address bus

• Identify the source or destination of data
• e.g. CPU needs to read an instruction (data) from
  a given location in memory
• Bus width determines maximum memory capacity of
  system
• e.g. 8080 has 16 bit address bus giving 64k
  address space

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Control Bus

• Control signals transmit both command and timing
  information between system modules.
• Timing signals indicate the validity of data and
  address information.
• Command signals specify operations to be
  performed.
• Control lines include the following
• Memory read/write signal
• I/O read/write signal
• Transfer ACK
• Bus request
• Bus grant
• Interrupt request
• Interrupt ACK
• Clock signals
• Reset

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• The operation of the bus is as follows
• If one module wishes to send data to another, it
  must do two things
• Obtain the use of the bus
• Transfer data via bus
• If one module wishes to request to the other
  module, it must do two things
• Obtain the use of the bus.
• Transfer a request to the other module over the
  appropriate control and address lines.

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Bus

• What do buses look like?
• Parallel lines on circuit boards
• Ribbon cables
• Strip connectors on mother boards
• e.g. PCI
• Sets of wires
• See Fig. (3.17)

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Single Bus Problems

• Lots of devices on one bus leads to
• Propagation delays
• Long data paths mean that co-ordination of bus
  use can adversely affect performance
• Bottleneck
• If aggregate data transfer demand approaches bus
  capacity
• Most systems use multiple buses to overcome these
  problems
• Local bus
• Connects the processor to a cache memory
• System bus
• Expansion bus

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Traditional (ISA)(with cache)
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High Performance Bus (mezzanine architecture)
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• Advantage
• The high speed bus brings high-demand devices
  into closer integration with processor
• Independent of the processor
• The difference in processor and high-speed bus
  speeds and the signal line definitions are
  tolerated

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Element of Bus Design

• Type
• Delicated
• Multiplexed
• Method of arbitration
• Centralized
• Distributed
• Timing
• Synchronous
• Asynchronous
• Bus width
• Address
• Data
• Data transfer type
• Read
• Write
• Read-modify-write
• Read-after-write
• block

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Bus Types

• Dedicated
• Functional dedication
• Separate data address lines
• Physical dedication
• The use of multiple buses, each of which connects
  only a subset of modules.
• Multiplexed
• Time multiplexing
• Shared lines
• Address valid or data valid control line
• Advantage - fewer lines
• Disadvantages
• More complex control
• A potential reduction in performance

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Bus Arbitration

• More than one module controlling the bus
• e.g. CPU and DMA controller
• Only one module may control bus at one time
• Arbitration may be centralised or distributed

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Centralised Arbitration

• Single hardware device controlling bus access
• Bus Controller
• Arbiter
• May be part of CPU or separate

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Distributed Arbitration

• Each module may claim the bus
• Each module contains access control logic
• See Fig. (3.26)

Bus
Bus Request
Bus Busy
Bus Grant
Device 1
Device 2
Device 3
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Timing

• Co-ordination of events on bus
• Synchronous
• Events determined by clock signals
• Control Bus includes clock line
• A single 1-0 is a bus cycle
• All devices can read clock line
• Usually sync on leading edge
• Usually a single cycle for an event

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Synchronous Timing Diagram
1. CPU??????????????
2. CPU??????
3.CPU?T2??????
1
4. ??????????????????????????
,
2
3. CPU?T2????????
4
4.??????, CPU??????
3
5.?T3???????????
5
3
4
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Asynchronous Timing Read Diagram
Asynchronous The occurrence of one event on a bus
follows and depends on the occurrence of a
previous event.
1
7
5
2
3
4
6
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Asynchronous Timing Write Diagram
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• Bus Width
• The width of the data bus has an impact on system
  performance
• The wider the data bus, the greater the number of
  bits transferred at one time
• The wider the address bus, the greater the range
  of locations that can be referrenced

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• Data transfer type

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PCI Bus

• Peripheral Component Interconnection
• Intel released to public domain
• 32 or 64 bit
• 50 lines

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PCI Bus Lines (required)

• Systems lines
• Including clock and reset
• Address Data
• 32 time mux lines for address/data
• Interrupt validate lines
• Interface Control
• Arbitration
• Not shared
• Direct connection to PCI bus arbiter
• Error lines

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PCI Bus Lines (Optional)

• Interrupt lines
• Not shared
• Cache support
• 64-bit Bus Extension
• Additional 32 lines
• Time multiplexed
• 2 lines to enable devices to agree to use 64-bit
  transfer
• JTAG/Boundary Scan
• For testing procedures defined in IEEE standard
  1149.1

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PCI Commands

• Transaction between initiator (master) and target
• Master claims bus
• Determine type of transaction
• e.g. I/O read/write
• Address phase
• One or more data phases

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PCI Read Timing Diagram
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PCI Bus Arbitration
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Foreground Reading

• Stallings, chapter 3 (all of it)
• www.pcguide.com/ref/mbsys/buses/
• In fact, read the whole site!
• www.pcguide.com/