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The ATLAS Pixel Detector

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... included two versions of FE (FE-D2D and FE-D2S) MCC, VDC and DORIC prototypes. ... DORIC continuing. First 0.25m Engineering run (MCC,FE,VDC,DORIC) ... – PowerPoint PPT presentation

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Title: The ATLAS Pixel Detector


1
  • The ATLAS Pixel Detector
  • Claudia Gemme INFN and University of Genova
  • on behalf of the ATLAS Pixel Collaboration

2
The ATLAS Pixel Detector
  • It is the innermost part of the silicon vertex
    tracker of the ATLAS experiment.
  • It consists of two parts
  • 3 barrel layers
  • 33 forward-backward disks
  • 2.0 m2 of sensitive area with 0.8 ? 108 channels
  • 50 ?m ? 400 ?m silicon pixels (50 ?m ? 300 ?m in
    the B-layer)

3
Insertable Layout
  • Pixel detector layout and design have been
    modified over the last year to cope with delays
    in radiation-hard integrated circuit electronics.
  • Pros
  • Complete Pixel detector can be inserted or
    removed with remainder of Inner Detector in
    place i.e. as late as possible for initial
    installation.
  • The insertable concept will also facilitate
    maintenance, repair and upgrades.
  • Reduced number of modules (-17)gt less time to
    produce them.
  • Transverse impact parameter resolution is
    similar to that expected by the previous layout.
  • Cons
  • Smaller external radius (14.2cm?12.2cm).
  • Worse material distribution (especially for high
    h).
  • 2 of tracks with less than 3 points.

4
Insertable Layout
  • 3 layers with radii 12.25 cm, 9.85 cm and 5.05 cm
    in the barrel.
  • Radiation doses at the radius of the middle layer
    in 10 years of LHC operation are expected to be
    1015 1-MeV neq/cm2 total dose 50 Mrad. This is
    the dose to which individual detector components
    are designed.
  • B-layer has particle flux 5 times higher than the
    middle layer it should be replaced every few
    years.

Barrel Transverse view
Longitudinal view
5
Local supports
  • Barrel staves and disk sectors are Local Supports
    that hold and cool pixel modules.
  • Many prototypes of Local Supports produced and
    tested (dimensional stability, thermal and
    pressure cycles) .
  • Production Readiness Review for Local Supports
    and Conceptual Design Review of rest of mechanics
    passed in July01.
  • The cooling fluid (C3F8) will flow in thin Al
    tubes (0.2mm) both for staves and disks. The Al
    tube in the staves has been introduced after
    roptures of the Carbon tube under very high
    pressure conditions (8 Atm).

6
Modules
  • Modules are the basic building elements of the
    detector (1456 in the barrel 288 in the
    end-caps).
  • Each module has an active area of 16.4 mm x 60.8
    mm.
  • The sensitive area is read out by 16 FE chips,
    each serving a 18 columns x 160 row pixel matrix.
  • The 16 FE chips are controlled by a Module
    Controller Chip (MCC).
  • A Flex-Hybrid circuit glued on the sensor
    backside provides the signal routing between the
    16 FE chips and the MCC. It also provides power
    routing for the FEs, MCC and sensor.

7
Electronics Overview
  • Four rad-hard ICs needed. Radiation hardness up
    to about 50 Mrad.
  • MCC decode data/cmd signals (from DORIC),
    generate control signal for FEs, collect data
    from FEs and accumulate in FIFOs, check event
    consistency, build module event and sends to DAQ
    (via VDC), handle errors and fault conditions.
  • FE chip control 18x160 pixels. Amplify sensor
    signal, on-chip data buffering in EOC FIFOs until
    trigger signal arrives, send data on serial link
    to MCC.
  • VDC drive data off detector.
  • DORIC regenerate clock and data/cmd signals.

8
Electronics history
  • Rad-soft FE and MCC successful and used for
    module testing, irradiated sensor testing and
    demonstrating that ATLAS specifications could be
    met.
  • Rad-hard FE development began with Atmel/DMILL in
    mid-98. These FE-D1 chips had very poor yield.
  • Second run with Atmel submitted in July 00 and
    included two versions of FE (FE-D2D and FE-D2S)
    MCC, VDC and DORIC prototypes. FE-D2D as FE-D1
    with bug fixed. FE-D2s modified design to remove
    circuit elements sensitive to technology problems
    but at cost of removing some functionality.
  • Yield of FE-D2S good enough to proceed to build a
    few active modules and single-chip. Single-chip
    devices tested at CERN H8 test beam (Aug01) and
    then irradiated. Next week they will be again at
    the H8 test beam to study irradiation effects.
  • Due to the unsolvable yield problems, design work
    stopped for FE and MCC in DMILL in Sept 00 and
    all efforts concentrated on 0.25m process (Deep
    Sub-Micron, DSM). DSM and DMILL design work on
    VDC/DORIC continuing.
  • First 0.25m Engineering run (MCC,FE,VDC,DORIC)
    foreseen in few weeks.

9
FE chip 0.25m
  • Dual process approach with TSMC/IBM.
  • First digital test chip submitted to TSMC in
    Jan01. Limited functionality but worked roughly
    as expected.
  • Analog test chip contains preliminary designs of
    analog blocks of 20 pixels and other critical
    analog items. Submitted to IBM and TSMC in
    Feb/Mar01.
  • TSMC chip delivered in May. IBM version
    (identical) delivered in July.
  • General features as expected (noise, timewalk,
    trim DACs,ToT) except for thresholdgt very large
    dispersion.
  • 1st irradiation with 55 MeV protons at very high
    dose rates (LBL cyclotron)
  • On-line results indicate little or no change in
    performance after 50 Mrad.

10
MCC-History
MCC-AMS - 1998
MCC-D2 - 2000
  • St. Cells FIFOs area (mm2)
  • MCC-AMS 18000 32 56
  • MCC-D2 13500 32 100
  • MCC-DSM 30000 128 25

MCC-DSM - 2001
11
Sensor
  • Baseline design
  • n pixel in n-bulk material
  • to operate partially depleted
  • double-sided processing.
  • Moderated p-spray isolation.
  • Bias grid to allow testing before module
    assembly.
  • Oxygenated silicon to improve radiation
    resistance and increase allowable time to room
    temperature (for repair/upgrades).
  • 3 sensor tiles per wafer.
  • Various test and monitoring structures.
  • PRR completed Feb 00.

12
Sensor preproduction results
  • Preproduction started in Aug00.
  • Two vendors
  • Cis preproduction complete. Test results show
    good quality and excellent correlation between
    our QC measurements and those done by CIS.
  • Tesla they have had yield problems, but now
    believes that are solved. More wafers in next
    months.
  • V_breakdown (the highest voltage for which the
    normalised current leakage current is lt 2mA)
    required to be gt 150V.
  • We found that none of the tiles ruled good by the
    manufacturers (and paid for) turned out to be bad.

13
Modules History
  • 98-99 Bare Module - MCC in package
  • 2000 Flex Hybrid 1.x Module with PCB card,
    MCC e Flex
  • 2001 Flex Hybrid 2.x - Module on CC support,
    no PCB card

14
Electronic Module Tests
  • Test a module to check for
  • connections of power, control and I/O signals
  • operation of the 16 FE chips
  • MCC communication protocol and event building
    capabilities
  • hybridization quality comparison between
    vendors (Alenia Marconi Systems In bumps, IZM
    PbSn bumps)
  • module performance (threshold, noise, bad
    channels).
  • Testing procedure
  • digital tests
  • analog tests
  • source measurements
  • test beam.

15
Analog Tests
  • Characterize threshold and noise of each channel
    by injecting a voltage signal in each pixel cell.
  • Threshold and noise at different steps in
    assembling
  • Tuning of threshold to have good uniformity in
    each FE chip
  • Threshold stability.

noise(e-)
Scan voltage(mV)
Threshold(e-)
16
Analogue Results Threshold Uniformity
Mean Threshold 3200e
Before tuning threshold dispersion 290 e
After tuning threshold dispersion 190 e
17
Analogue Results Threshold Stability
  • Both for AMS and IZM modules, the threshold
    distribution tends to drift by a few hundred
    electrons between threshold scans.

18
Noise plot
  • Overall module noise 145 e
  • Larger noise for pixel in column0 (pixel area 50
    x 600 mm2).
  • Ganged pixels two diodes connected to the same
    readout cell in the interchip region.

19
Bad channels plot
  • In this module 21 bad channels (16 merged, 5
    inefficient)
  • Merged channels (i.e. bad channels coupled with a
    very noisy pixel) 0.1 i.e. 2 pixels/FEchip
  • Missing channels (i.e. good electronics pixels
    but no signal with source) 2 10-5

c0,r159
5
6
20
Conclusions
  • The ATLAS Pixel Collaboration is approaching
    pre-production and production for many items of
    the detector.
  • Detector layout has been modified to cope with
    delays of radiation-hard integrated circuit
    electronics.
  • Next year
  • Begins production of sensors, Local Supports and
    mechanical structures.
  • DSM electronics evaluation of first prototypes,
    second iteration.
  • Modules production of 50 dummy modules per each
    of bump bonding vendors. They will be used to
    test the assembly procedure and to evaluate
    thermal and mechanical stresses.
  • Flex Hybrid third generation prototype design
    completed, compatible with DSM chips.

21
Material
  • To minimize material
  • 250 mm thick sensor
  • Electronics thinned to 150 mm
  • all supports in carbon composite material it is
    ultra stable and ultra light (4.4Kg)
  • Asymmetric distribution of material B-layer
    services exit on one side.

22
Coverage
  • Coverage of the insertable layout
  • Probability to have less than 3 layer hits
  • 1.5 hlt1.5 (barrel)
  • 2.5 hlt2.5 (end-caps)
  • Almost independent of particle energy (down to
    0.4 GeV)
  • Inability to have first disk close enough to
    barrel.
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