Compiling Esterel into Sequential Code

1
Compiling Esterel intoSequential Code

• Stephen Edwards

Advanced Technology Group
2
An Application
CoCentricTM System Studio
Control
Dataflow
Esterel
Dataflow Compiler
This work
C
C
Compiled Simulation
3
The Esterel Language
4
The Esterel Language

• Developed by G. Berry et al. starting 1983

5
The Esterel Language
emit B if C emit D
Force signal B to be present in this cycle
Emit D if signal C is present
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The Esterel Language
await A emit B if C emit D
pause
Wait for next cycle with A present
Wait for next cycle
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The Esterel Language
loop await A emit B if C emit
D pause end
Infinite loop
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The Esterel Language
loop await A emit B if C emit
D pause end loop if B emit C
pause end
Run concurrently
9
The Esterel Language
loop await A emit B if C emit
D pause end loop if B emit C
pause end
Same-cycle bidirectional communication
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The Esterel Language
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
Restart when RESET present
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The Esterel Language
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
Good for hierarchical FSMs
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The Esterel Language
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
Bad at manipulating data
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New Compiler
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The New Compiler
Esterel
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
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The New Compiler
Esterel
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
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The New Compiler
Esterel
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
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The New Compiler
Esterel
C
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
Void foo() switch (st) 0 if (IN3)
st 5 goto L5 1 if (RES)
st 3 goto L8 L5 switch
Step 4 Generate C
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The New Compiler
Esterel
C
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
Void foo() switch (st) 0 if (IN3)
st 5 goto L5 1 if (RES)
st 3 goto L8 L5 switch

• Generated code is 2 to 100? faster
• 1/2 to 1? the size

Concurrent Control-Flow Graph
Sequential Control-Flow Graph
Scheduled CCFG
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The New Compiler
Esterel
C
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
Void foo() switch (st) 0 if (IN3)
st 5 goto L5 1 if (RES)
st 3 goto L8 L5 switch
Flow similar to Lin DAC 98
Concurrent Control-Flow Graph
Sequential Control-Flow Graph
Scheduled CCFG
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Step 1 Build Concurrent CFG
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
RESET
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Add Threads
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
RESET
Fork
Join
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Split at Pauses
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
RESET
1
1
s
2
2
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Add Code Between Pauses
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
RESET
1
s
2
A
B
C
D
s2
s1
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Build Right Thread
every RESET do loop await A emit B
if C emit D pause end loop if B
emit C pause end end
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Step 2 Schedule
Add arcs for communication
RESET
Topological sort Optimal scheduling
NP-Complete Bad schedules OK
1
s
2
A
B
B
C
C
D
s2
s1
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Step 3 Sequentialize

• Hardest part Removing concurrency
• Simulate the Concurrent CFG
• Main Loop
• For each node in scheduled order,
• Insert context switch if from different thread
• Copy node connect predecessors

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Context Switching Code
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Run First Node
RESET
RESET
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Run First Part of Left Thread
RESET
1
s
2
B
1
s
A
2
A
B
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Context switch Save State
RESET
1
s
2
B
A
t0
t1
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Rejoin
RESET
1
s
2
B
A
t0
t1
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Run Right Thread
RESET
1
s
2
B
A
t0
t1
B
B
C
C
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Context Switch Restore State
RESET
1
s
2
B
A
t0
t1
B
C
0
1
t
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Resume Left Thread
RESET
1
s
2
B
A
t0
t1
B
C
C
0
1
t
D
D
C
s2
s1
s2
s1
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Step 3 Finished
RESET
RESET
1
s
2
B
1
s
A
2
A
t0
t1
B
B
B
C
C
C
0
1
t
D
D
C
s2
s1
s2
s1
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Related Work and Experiments
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Existing Esterel Compilers
Capacity
Simulation Speed
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Existing Esterel Compilers
Capacity
Automata V3 Berry 87, Polis DAC 95
Simulation Speed
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Existing Esterel Compilers
Logic gates V4, V5 Berry 92, 96
Capacity
Automata V3 Berry 87, Polis DAC 95
Simulation Speed
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Speed of Generated Code
Average cycle time (ms)
Size (source lines)
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Size of Generated Code
Object code size (K)
Size (source lines)
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Why This Wins
Automata
Zero overhead Code duplicated
Gates
No duplication Not event driven runs idle
code Significant overhead
New
Only active code runs No code duplication
Some overhead
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Why Not Event-Driven?

• Already exclusively running active code
• Behavior of event queue is simulated once at
  compile-time and hardwired
• Technically difficult for Esterel
• Netlist includes mixture of event and
  level-sensitive entities

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Summary

• Esterel
• Deterministic concurrency
• Good for hierarchical FSMs
• New Compiler
• Build concurrent control-flow graph
• Schedule
• Sequentialize add context switches
• Results
• Code runs 2 to 100? faster
• 1 to 1/2 the size