Advanced Topics in Power Consumption Reduction

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Advanced Topics in Power Consumption Reduction

• -Lakshmi Easwaran

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Dynamic Voltage Scaling for Commercial FPGAs

• C.T. Chow1, L.S.M. Tsui1, P.H.W. Leong1,2, W.
  Luk2, S.J.E. Wilton3
• 1Dept. of Computer Science and Engineering, The
  Chinese University of Hong Kong
• 2Dept. of Computing, Imperial College London
• 3Dept. of Electrical and Computer Engineering,
  University of British Columbia
• ctchow, lstsui2_at_cse.cuhk.edu.hk, phwl,
  wl_at_doc.ic.ac.uk, stevew_at_ece.ubc.ca

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Contributions

• Dynamic voltage scaling for reducing FPGA power
  consumption
• A Logic Delay Measurement Circuit using FPGA
  resources
• Achievement of power reductions from 4 to 54

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Components of Power

• Static power
• Due to leakage power
• Dynamic power
• due to charging n discharging of capacitances in
  the circuit
• main source of power consumption
• P ?(C Vdd 2 f)

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Methods of Power Reduction

• Methods that involve changing fpga architecture
• Power aware fpga architectures
• Dynamic clock management
• Methods that do not involve changing fpga
  architecture
• Pipelining long combinational circuits
• Dynamic power is reduced
• Power consumption is reduced by 40-90
• Power aware CAD algorithms

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Dynamic Voltage Scaling (DVS)

• Voltage scaling involves reducing the supply
  voltage of a circuit.
• Reduces dynamic and leakage current
• Increases the circuit delay
• Closed loop ctrl to prevent over reduction of
  voltage

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Basic Idea

• A logic delay measurement circuit (LDMC)
• determine the speed of an inverter chain at run
  time.
• A desired LDMC value a safety margin
• A closed loop control scheme to maintain the
  desired LDMC
• by automatically adjusting the voltage applied to
  the FPGA.

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System Architecture of DVS implementation.

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Dynamic Voltage Scaling Architecture

• FPGAs have separate supply networks for
• Input output blocks Vio
• not modified in order to maintain compatibility
  with other chips at the board level
• Internal circuit Vint
• logic cells, routing elements and storage cells
  
• We apply DVS to this  

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Voltage Controller

• Ensures the voltage supply to the FPGA is not
  lowered so much that the FPGA ceases to operate
  properly.
• The following errors can occur if voltage is
  operated below a threshold value
• IO error
• DELAY error

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Example of IO error in DVS

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Delay as a function of supply voltage
Figure shows regions where the circuit will
operate correctly and where it will fail.
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Schematic of the LDMC
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Placement of LDMC
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Voltage Control Algorithm

• Voltage InitialVoltage
• while true
• do
• if ((LDMC - Threshold) gt 8)
• Voltage Voltage - 0.05
• elseif ((LDMC - Threshold) gt 3)
• Voltage Voltage - 0.01
• elseif ((LDMC - Threshold) gt 0)
• Voltage Voltage - 0.005
• elseif ((LDMC - Threshold) 0)
• Voltage remain unchanged
• elseif ((LDMC - Threshold) lt 0)
• Voltage Voltage 0.01
• wait for 200 ms
• done

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Threshold Value

• Dynamic threshold
• Threshold when whether the voltage changes
  quickly
• Static threshold
• Threshold when whether the voltage changes
  quickly

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Threshold Value

• Threshold max(THds, THdd, THis, Hid)THsm
• Where
• THds is the static delay threshold,
• THdd is the dynamic delay threshold,
• THis is the static IO threshold value,
• THid is the dynamic IO threshold value,
• and THsm is a safety margin
• THsm 2 works from experiments.
•  

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Experiments

• The board contains a Xilinx Virtex 300E-8 device,
  which contains a 3248 CLB array implemented in
  0.18µm with 6-layer metal CMOS technology.
• Experiments done to
• demonstrate correlation between LDMC readings and
  (i) IO errors, and (ii) delay errors.
• Power savings and the trade off between
  throughput, power consumption and area using the
  DVS technique

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Block Diagram of IO Error experiment
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IO Static Threshold Value and Voltageas a
function of circuit activity
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Architecture of test circuitto detect
occurrence of delay error
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Static and Dynamic Delay Thresholds
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Tolerance

• The amount by which we can slow down the circuit,
  by reducing the supply voltage before the circuit
  fails to meet timing requirements.
• Tolerance (P1 - P2)/P2
• where
• P2 is the minimum operating period reported by
  the vendor tool,
• and P1 is period of the clock used to test the
  circuit
• in general, P2 lt P1 for a circuit operating
  correctly

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Impact of Chip Temperature on VINT
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Power reduction achieved using DVS
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Observations

• Circuits having a LDMC threshold near the IO
  error LDMC threshold have the best power
  reduction.
• Circuits with larger tolerance usually have large
  power savings so a maximum pipelining results in
  the largest power savings.
• Pipelining can reduce the power consumption even
  if voltage scaling technique is not applied

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Tradeoff between Throughput, Energy and Area
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Summary

• Overall power reduction upto 54 is achieved
• This method does not require changes to the
  design of the circuit. So it can be applied after
  the circuit is developed.
• Can be combined with other techniques like
  pipelining to get additional power reduction
•  

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Power Consumption Reduction Through Dynamic
Reconfiguration
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Dynamic Reconfiguration 

• Optimizes the use of hardware resources, and
  therefore may produce important reductions in
  power consumption
• Objective of this paper is to evaluate the
  reconfiguration power consumption
• Quantifies the tradeoff between the energy saved
  by the use of dynamic reconfiguration and the
  energy wasted by the reconfiguration process.
• Reconfiguration at the highest frequency
  available reduces power consumption.

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Power Components 

• Dynamic power
• Depends on capacitance on frequency
• Expected to be similar in reconfigurable and
  non-reconfigurable system
• Static power
• Less power consumption in reconfigurable system
• For a k times smaller device, static power
  consumption reduces by the same amount
• Power consumption due to the reconfiguration
  process

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Power Consumption during Dynamic Partial
Reconfiguration (Atmel AT40K20 FPGA)
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Average Power Calculation

• Reconfigurable device AT40K20 FPGA from ATMEL
  used for experiments
• Can be dynamically reconfigured for any number of
  cells.
• Reconfiguration power consumption
  Instantaneous power consumption is measured and
  average power is computed.

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Average Power Calculation
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Reconfiguration Energy Consumption
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Configuration Power Consumption
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Cells Configuration Power Consumption
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Cells Configuration Power Consumption

• Instantaneous power consumption a freq
• The well-known equation of consumption in CMOS
  circuits is
• P?IleakVDD ? KiVDDISC ? CiVDD2Fi
• Last term gt dynamic power (at high freq, this
  dominates)
• First term gt static power (at low freq, this
  dominates)

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Configuration Power Consumption of
Interconnections
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Configuration Power Consumption of
Interconnections
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Configuration Energy Consumption
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Cells Configuration Energy Consumption
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Interconnections Configuration Energy
Consumption
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Conclusions from Experiments

• Energy wasted during the reconfiguration process
• dominated by short-circuit and static power
  consumption.
• These power components increase with time.
• So reconfiguration must be made at higher
  frequency available to reduce the power
  consumption.

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Comparison of Energy of Reconfigurable System
with a Conventional System 

• Total Energy required by a reconfigurable system
  is
• E Total_Reconfiguratión EStatic EDynamic K
  Ereconfiguration
• where E Reconfiguration is the average energy
  wasted for a single reconfiguration.
• Energy required by a non-reconfigurable system
  is
• Etotal N.Estatic EDynamic

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Continued..
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Continued..

• With the data presented in the previous section,
  measured for the Atmels FPGAs, we get
•  Tprocess gt 1.4 .
  Preconfiguration 16
• treconfiguration
  Pstatic
•  For this example,
• reconfiguration time is 15 ms for reconfiguration
  at 16 MHz.
• The reconfigurable system will be power
  profitable if
• the processing time for each process is at least
  240 ms.
• In a typical dynamically reconfiguration system
  for image processing ,
• processing time 23 reconfiguration time.
•  

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Summary

• Dynamic reconfiguration produces reductions in
  power consumption.
• Reconfiguration power has been characterized to
  determine the power reduction that can be
  obtained by using dynamic reconfiguration in a
  design.
• Power savings will be obtained if a sufficient
  ratio of processing time to reconfiguration time
  is achieved.
• Reconfiguration must be made at the highest
  frequency available to reduce power consumption