RAM Basics

1
RAM Basics

• Anselmo Lastra

2
Topics

• VGA timing project
• Deadline Thursday
• Class time change
• Semester project topics
• RAMs

3
Class Time

• Preference for keeping TTh
• Unfortunately, no open time for all

4
Projects

• Some have project already
• Polygon pipeline
• Stopping points Gouraud, texturing, etc.
• Ray caster/tracer
• Similar possible milestones
• Can share common parts

5
Simple Hdw View of RAM

• Some capacity 2k
• k bits of address lines
• Often multiplexed
• Maybe have read line, clock, chip select
• Have a write enable line

6
Reading

• Setup address lines
• Activate enable, read/write line
• Data available after specified amt of time

7
Writing

• Setup address lines
• Setup data lines
• Activate write line

8
Static vs Dynamic RAM

• SRAM vs DRAM
• DRAM stores charge in whats essentially
  capacitor
• Disappears over short period of time
• Must be refreshed (rewritten/recharged)
• SRAM easier to use
• Faster
• More expensive per bit
• Smaller sizes

9
Structure of SRAM

• Control logic
• One memory cell per bit
• Cell consists of one or more transistors
• Not really a latch made of logic
• Logic equivalent

10
Bit Slice

• Cells connected to form 1 bit position
• Word Select gates one latch from address lines
• Note it selects Reads also
• B (and B not) set by R/W, Data In and BitSelect
• Funny thing here when you write. What is it?

11
Bit Slice can Become Module

• Basically bit slice is a X1 memory
• Next

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16 X 1 RAM

• Now shows decoder

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Tri-State

• Have three states H, L, and Hi-Z
• High impedance
• Behaves like no output connection if in Hi-Z
  state
• Allows connecting multiple outputs

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Multiplexed with Hi-Z

• Normal behavior is blue area

15
Row/Column

• If RAM gets large, there is a large decoder
• Also run into chip layout issues
• Larger memories usually 2D in a matrix layout
• Next Slide

16
16 X 1 as 4 X 4 Array

• Two decoders
• Row
• Column
• Address just broken up
• Not visible from outside

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Change to 4 X 2 RAM

• Minor change in logic
• Also pinouts

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Realistic Sizes

• Imagine 256K memory as 32K X 8
• One column layout would need 15-bit decoder with
  32K outputs!
• Can make a square layout with 9-bit row and 6-bit
  column decoders

19
SRAM Performance

• Current ones have cycle times in low nanoseconds
  (say 2.5ns)
• Used as cache (typically offchip secondary cache)
• Sizes up to 8Mbit or so for fast chips

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Using SRAM on Spartan II

• Recall block SRAM available on chip
• 11 4Kb blocks
• Configured in many ways (table)

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Using from Verilog

• Instantiate a block (here called R1)
• RAMB4_S8_S8 R1 (.DOA (data_a),
• .DOB (data_b),
• .ADDRA (addr_a),
• .ADDRB (addr_a),
• .CLKA (clk),
• .CLKB (clk),
• .DIA (data_in),
• .DIB (data_in),
• .ENA (ena),
• .ENB (enb),
• .RSTA (rsta),
• .RSTB (rstb),
• .WEA (wea),
• .WEB (web))

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Can Initialize

• Have to do it two ways, one for simulator,
  another for hardware
• //synthesis attribute INIT_00 of R1 is
  "08192A3B4C5... total of 256 bits (64 hex
  characters)..."
• //synthesis attribute INIT_01 of R1 is
  "08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F0
  8192A3B4C5D6E7F
• // Up to INIT_0F
• Above is for hardware (next software)

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For Simulation

• //synopsys translate_off
• defparam R1.INIT_00 64'h08192A3B4C5D6E7F08192A3B
  4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F //
  256-bit hex value
• defparam R1.INIT_01 64'h08192A3B4C5D6E7F08192A3B
  4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F //
  256-bit hex value
• ...
• defparam R1.INIT_0F 64'h08192A3B4C5D6E7F08192A
  3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F // up
  to INIT_0F
• //synopsys translate_on

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Look at Test Code

• My RAM loading example from undergrad class
• http//www.cs.unc.edu/lastra/comp190/Assignments/
  block_ram_C.txt

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Dynamic RAM

• Capacitor can hold charge
• Transistor acts as gate
• No charge is a 0
• Can add charge to store a 1
• Then open switch (disconnect)
• Can read by closing switch
• Explanation next

26
Precharge and Sense Amps

• Youll see precharge time
• B is precharged to ½ V
• Charge/no-charge on C will increase or decrease
  voltage
• Sense amps detect this

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DRAM Characteristics

• Destructive Read
• When cell read, charge removed
• Must be restored after a read
• Refresh
• Also, theres steady leakage
• Charge must be restored periodically

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DRAM Logical Diagram
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DRAM Read Signaling

• Lower pin count by using same pins for row and
  column addresses

Delay until data available
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DRAM Write Timing
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DRAM Refresh

• Many strategies w/ logic on chip
• Here a row counter

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CAS Before RAS

• Set column address
• Apply CAS first (opposite of RW)
• Then toggle RAS enough times to cycle through row
  addresses
• On-board refresh counter applies the row addresses

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Timing

• Say need to refresh every 64ms
• Distributed refresh
• Spread refresh out evenly over 64ms
• Say on a 4Mx4 DRAM, refresh every 64ms/409615.6
  us
• Total time spent is 0.25ms, but spread
• Burst refresh
• Same 0.25ms, but all at once
• May not be good in a computer system
• Refresh takes 1 or so of total time

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Larger/Wider Memories
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Bidirectional Lines

• One set of data pins
• Used as input for write
• As output for read
• Tri-state
• Makes sense because dont need both at once

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Page Mode DRAM

• DRAMs made to read write blocks
• Example
• Assert RAS, leave asserted
• Assert CAS multiple times to read sequence of
  data
• Similar for writes

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Synchronous DRAM (SDRAM)

• Common type in PCs late-90s
• Burst transfers
• Multiple banks
• Pipelined
• Start read in one bank after another
• Come back and read the resulting values one after
  another

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SDRAM on Xess Board

• Relatively small at 128Mbits
• 2M X 4 banks X 16 bits
• Refresh every 64ms
• Supports pipelining
• Bidirectional data lines
• Detailed info in a few slides

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DDR DRAM

• Double Data Rate SDRAM
• Transfers data on both edges of the clock
• Currently popular

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RAMBUS DRAM (RDRAM)

• Another attempt to alleviate pinout limits
• Many (16-32) banks per chip
• Made to be read/written in packets
• Up to 400MHz bus speeds
• But DDR doing very well also

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DRAM Controllers

• Very common to have circuit that controls memory
• Handles banks
• Handles refresh
• Multiplexes column and row addresses
• RAS and CAS timing
• Northbridge on PC chip set

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Next Specifics on Our Chip

• Protocol for reading/writing
• Activate row first
• Then read/write with column
• Initialization
• Setting parameters

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Block Diagram
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Activate Row
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Read (Select column)
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Burst Reads
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Read with Autoprecharge
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Read w/o Autoprecharge
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Random Reads
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Alternating Banks
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Single Write
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Initializing

• See P.9 of Micron datasheet
• Just NOP commands for 100 us
• Precharge all banks
• Two Auto Refresh commands
• Then load mode register

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Mode Register

• Several operating modes of SDRAM

1,2,4,8 or full page
Burst or single
2 or 3
Order or accesses
0
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DRAM Links

• DRAM on XSA-100 board
• http//www.hynix.co.kr/datasheet/pdf/dram/(2)HY57V
  281620A(L)T-I.PDF
• Low-Tech RAM description
• http//www.arstechnica.com/paedia/r/ram_guide/ra
  m_guide.part1-1.html
• Datasheets
• http//www.hynix.co.kr/datasheet/pdf/dram/(2)HY57V
  281620A(L)T-I.PDF
• http//download.micron.com/pdf/datasheets/dram/128
  msdram_f.pdf
• http//www.infineon.com/cmc_upload/documents/018/3
  29/hb39s128CT.pdf
• Verilog model
• http//download.micron.com/downloads/models/verilo
  g/sdram/sdr/128meg/mt48lc8m16a2.zip

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Assignment

• Try Block RAM
• Maybe to scan small stamps
• Or as character/sprite device
• Make DRAM controller to refresh screen
• Deadline end of next week

56
Next Time

• Thursday 9/11 read Kurt Akeley, "Reality Engine
  Graphics", SIGGRAPH 93
• Link is
• http//doi.acm.org/10.1145/166117.166131