Interrupts and DMA

1
Interrupts and DMA

• Anselmo Lastra

2
Interrupts

• Two main kinds
• Internal
• Error when executing an instruction
• Floating point exception
• Trying to access protected memory
• System call
• To request OS services
• External
• I/O

3
Internal

• More complicated because may abort instruction
• Or OS could correct the situation
• Example Access to protected memory not allowed

4
When Interrupt Occurs

• Interrupt enable register
• Sometimes levels of interrupts individually
  enabled/disabled
• PC is changed to new location
• One or more interrupt locations stored
• Or a fixed location
• Old PC saved to register or stack
• Many machines have stack pointer

5
Registers

• Sometimes registers saved by hardware
• Some machines have one or more sets of registers
• Other architectures software must save registers
• Sometimes instruction to return from interrupt

6
Cause of Interrupt

• Need way to determine what caused interrupt
• Note it can be more than one thing
• Vectored Interrupts
• Different types cause branches to different
  locations
• Sometimes prioritized
• Register to store cause

7
Supervisory Mode

• Modern computers have user mode and one or more
  supervisory modes
• User mode restricted
• Cant write to many system registers, such as
  interrupt enable
• Cant write to some parts of memory
• Usually I/O restricted
• Interrupts cause switch to supervisory mode

8
Some Interrupt Hardware

• Interrupts ORed
• Response if IE and at end of instruction
• Ack interrupt
• Vector address to PC
• PC to stack

9
Potential Microcode

• SP ? SP 1
• MSP ? PC
• SP ? SP 1
• MSP ? PSR
• PSR is processor status register
• EI ? 0
• INTACK ? 1
• PC ? IVAD

10
Return Similar

• Very similar to return from procedure
• PSR holds IE bit
• Restoring PSR turns interrupts on

11
From Patterson Hennessey
Branch to fixed addr
12
Direct Memory Access (DMA)

• Programmed I/O is when CPU reads/writes every
  word
• Problem overhead is high nothing else getting
  done on CPU
• Especially for mass-storage devices like disk
• DMA Let device controller read/write directly
  to memory

13
Procedure

• DMA device takes over main bus
• Becomes bus master
• Asserts addresses
• Basically interfaces to memory or memory
  controller

14
How?

• DMA device requests bus (assert BR)
• CPU grants request (assert BG)
• CPU takes its signals to Hi-Z

15
Transfers

• Continuous DMA controller transfers all data
  (say a disk sector) at once
• As many memory cycles as data
• Burst DMA controller cycle steals, takes a
  cycle at end of every CPU instruction

16
End of DMA

• Controller needs to inform CPU
• De-assert BR
• Then CPU lowers BG and proceeds

17
DMA Controller

• Needs typical I/O signals
• Interrupt request
• Status of device
• Also needs controls for DMA transfer
• Memory address
• Word count

18
Block Diagram
19
Typical Driver Interface

• Set the memory address
• Set word count
• Assert GO (usually bit in control word)
• DMA controller requests interrupt when transfer
  complete