Direct Memory Access DMA

1
Direct Memory Access (DMA)

• Direct Memory Access (DMA) - device other than
  processor controls transfer of data between
  memory and an I/O device contrast with
  processor/memory accesses and I/O instructions
• A DMA controller, or DMAC, is specialized logic
  (processor) that is optimized for the task of
  transferring data between I/O devices and memory
  without involving main processor (CPU)
• A DMA channel is the set of control and data
  lines a DMA controller uses to perform the
  transfer of data
• a DMA controller can have multiple channels so
  DMA accesses can be performed for multiple
  devices (but only one at a time, and only for a
  set of similar devices)

2
DMA (cont.)

• At minimum, a DMA operation needs the channel
  number (which I/O device requires the DMA), a
  beginning address in memory for the transfer, the
  number of bytes to transfer, and the direction of
  transfer (I/O to memory, or vice-versa)
• The processor kicks off the DMA activity with an
  ordinary I/O write to a control register in the
  DMA controller, then continues fetching and
  executing instructions as usual
• When DMA activity is finished, DMA controller
  interrupts the processor, resulting in execution
  of ISR for the DMAC
• DMAC more efficiently transfers data blocks
  between I/O device and memory than the CPU (why?)
  -- also, the CPU is freed to perform other tasks
  (overlapped or concurrent)

3
DMAC Connection
4
3 Modes of DMA Operation
Byte
Burst
Block
5
Bus Mastership

• DMA is an example of where the central processor
  or CPU turns control of the bus over to another
  device (a DMAC)
• A device that has control of a bus, up until now
  the CPU, is known as a bus Master memory
  components and non-DMA I/O devices are known as
  bus slave components
• In early system busses, only processor and a DMAC
  could have ownership of bus (i.e., become the Bus
  Master)
• Modern system busses (e.g. PCI) allow any I/O
  device to become bus master an I/O device that
  can become the bus master can perform DMA itself
  instead of using a DMAC
• If all I/O cards can become bus master then dont
  need a separate DMA controller each card is a
  DMAC

6
Bus Arbitration

• A piece of control logic known as the arbiter
  must decide which device gets ownership of the
  bus this control logic resides in the system
  chipset and is a part of the overall system bus
• Two lines are used for each peripheral that can
  become bus master
• Bus Request used by device to ask for control
  of bus (arbiter input)
• Bus Grant used by arbiter to grant bus to
  device (arbiter output)
• A peripheral typically has control of bus for a
  maximum number of clock cycles (typically 32)
  before it must release bus to the arbiter.
• Bus is a shared resource, shared by potential bus
  masters priorities are necessary for multiple
  requests similar to interrupt priorities

7
Bus Arbiter
Arbiter
Br
Bg
Br
Bg
Br
Bg
Device 1
Device 2
Device
Local Bus, e.g PCI
Number Br/Bg pairs determines maximum number
devices on bus (i.e. slots on bus) Br Bus
request and Bg Bus grant
8
Bus Terms, Glossary

• A Bus is a mechanism for multiple devices to
  talk to one another (to transfer data,
  synchronize, etc.)
• When one device talks, all others hear
• Data can be transmitted over bus in parallel or
  serially
• USB, IEEE Firewire are examples of serial busses
• PCI, ISA, SCSI are examples of parallel busses
• Bus may support only one master, or multiple
  masters
• If support multiple bus masters, must either
  support bus arbitration to decide master or
  schedule the bus accesses among the multiple
  masters (time division multiplexing)
  asynchronous vs synchronous sharing

9
Typical PCI Based x86 Computer Architecture
10
AMD Motherboard
11
Bus Terms, Glossary (cont.)

• The system bus is the bus that connects directly
  to pins of the processor also known as processor
  bus.
• These days, system bus only has cache memory and
  the system chipset connected to it
• Multiple processors may connect to system bus
• The system chipset will transfer data between the
  system bus and any other busses that make up the
  system (will act as a bridge between system bus
  and other busses).

12
Bus Terms, Glossary (cont)

• A local bus is a bus that stays inside the box
  (cards plug into the bus via slots on
  motherboard), forms a high speed path between
  memory and peripherals
• Will be a high bandwidth bus (wide and fast --- a
  parallel bus that is clocked at high rate)
• lines (address, control, data) run a short
  distance
• The PCI bus is an example of a local bus system
  chipset connects PCI bus to processor (system)
  bus.

13
Bus Terms, Glossary (cont)

• A peripheral bus is a bus that goes outside the
  box to connect peripherals to memory.
• Will NOT be as high bandwidth as system bus
  (slow)
• Will support a wide range of speeds (flexible)
• Can be either serial (Firewire, USB) or parallel
  (SCSI)
• lines can run long distance compared to system
  busses
• Firewire, USB, SCSI (for disks, scanners,
  CDROMs), EIDE (for disks, CDROMs) are peripheral
  busses.