Gauri Kulkarni

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Gauri Kulkarni

• Graduate Project Presentation
• Dept. Of Electrical Engineering,
• San Jose State University.

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Comparison of two logic techniques in a High
Speed Frequency Divider/Prescalar

• TSPC Technique and Two phase Clocking Technique

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Objective

• To compare two logic techniques using D
  Flip-Flops in a High Speed dynamic Prescalar.
• Analyze the performance in terms of Speed, Area,
  Ease of implementation and Design and Power
  consumption.
• Techniques used-TSPC and Two Phase Clocking
  Scheme.

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IntroductionFrequency Synthesizer

• 3 types by 2 counter, Dual modulus Prescalar,
  divide by N counter
• by 2 has highest operating frequency, limited
  as divide by 2M stages
• Dual Modulus-next high frequency as load is low.
  Ratio of N/N1
• Divide by N -N arbitrary

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Introduction - continued.

• Prescalar/frequency divider consists of a
  synchronous counter, an asynchronous counter and
  a modulus control circuit.
• Many logic styles available Standard
  Dynamic,NORA,ZIPPER,DOMINO, TSPC and Two phase
  clocking, DCVSL,CPL,CVSL etc.
• Comparison of TSPC and two phase clocking scheme

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Pseudo NMOS Logic

• Consists of resistive load type pull up and pull
  down network
• Small pull-up than static gate
• pull down longer as pull up is fighting

Vdd
a
b
gnd
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Pseudo Inverters
clk
D
O/P
O/P
O/P
D
clk
clk
clk
D
D
O/P
Pseudo-PMOS
Pseudo-NMOS
N-C?MOS
P-C?MOS
inverter
inverter
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TSPC technique

• Consists of Precharge and Evaluate with a single
  clock signal
• Easier to route
• No clock skew
• Fast
• Original DFF based on P-C²MOS, N precharge,
  N-C²MOS stages
• New fast DFF based on pseudo-NMOS,N-precharge and
  pseudo-PMOS inverter

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Results and Conclusion of the comparison between
the two techniques
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Comparative Results Ref 6