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Machine Description for Retargetable Compiler Backend

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Title: Machine Description for Retargetable Compiler Backend


1
Machine Description for Retargetable Compiler
Backend
  • Wei Qin
  • Nov, 2000

2
Outline
  • Motivation
  • Necessary information for compiler backend
  • Machine view
  • Instruction view
  • Machine Description
  • HMDES
  • Machine
  • Instruction
  • Conclusion

3
Motivation Compiler Backend
4
Motivation- Compiler Backend
  • Traditional compiler backends are mostly hand
    written.
  • Mescal design flow requires that the compiler
    retarget itself.
  • The architect should provide enough information
    to drive the backend.
  • A formal language between the architect and the
    compiler not English.

5
Motivation Compiler Backend
  • Mescal uni-processor compiler backend
  • Framework all in Xcode
  • Xcode IR input from front end
  • Xcode output to Liberty simulator
  • Have been done
  • HMDES, for scheduler
  • To do
  • Direct mapping code generator
  • Register allocation
  • Code optimization

6
Machine Description Instruction
  • Compilers view of instructions
  • Instruction format, i.e. and type of src, dest,
    predicate, constraints
  • Instruction function what the instruction does
  • For control/dataflow analysis (category of the
    instruction)
  • For functional simulator
  • Instruction behavior
  • Resource usage spatial and temporal

7
Machine Description-Machine
  • Compilers view of machine
  • General architecture information
  • Bus Widths
  • FU mix
  • register file number and size, overlapping
  • Specialty
  • Special registers
  • Delay slots

8
Machine Description- Part 1
  • High level machine description language
  • Resources register banks, issue slots, FUs
  • Operations format, resource usage, latency
  • Flags for compiler, mainly indicating category
    of instructions (control flow, memory operation)
  • Ref J. Gyllenhaal, W. Hwu, B. Rau, HMDES Version
    2.0 Specification IMPACT Technical Report, UIUC,
    IL 1996.

9
Machine Description Part 2
  • Machine Information
  • Macro registers SP, IP, OP, LV, ST
  • Data memory alignment, data type sizes,
    endianness (mspec file in IMPACT)
  • Number of delay slots, nullification
  • Function calling convention
  • Instruction sizes

10
Machine Description Part 3
  • HMDES provides a instruction list and the
    instruction formats and categories (by compiler
    flag), but little about functionality
  • Machine code description
  • One one mapping no need to specify
  • Most should fall in here since X code space is
    already big
  • One Many mapping
  • E.g. compare and branch
  • Optimization
  • One one mapping, e.g. move zero and xor
  • Many one mapping, e.g. Complex ALU, CISC memory
    op
  • Special instructions e.g. multiple load/store
    instruction

11
Machine Description Part 3 (contd)
  • Operand constraint
  • 3 address or 2 address
  • E.g. Thumb instruction set of Strong Arm
  • Binding to macro register
  • Illegal field
  • Functionality

12
Conclusion
  • Architect needs to provide machine information
    from various views
  • HMDES needs to be accompanied by the more
    detailed instruction view and machine view
  • XML can be used as a media
  • XML version of HMDES is there
  • Need semantics
  • Information complete?
  • Do the best we can
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