Machine Description for Retargetable Compiler Backend

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Machine Description for Retargetable Compiler
Backend

• Wei Qin
• Princeton University

2
Outline

• Motivation
• Machine Description
• Machine Code Description
• HMDES
• Miscellaneous ISA Details
• Conclusion

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Motivation Big picture
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Motivation Compiler Back End

• Traditional compiler (including IMPACT) back ends
  are mostly hard coded for specific architecture.
• Mescal designer does architecture exploration no
  pre-specified architecture.
• Compiler back end needs to be rewritten in a
  retargetable fashion.
• Architect should provide information from various
  views to drive the backend.
• A formal language between the architect and the
  compiler.

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Motivation Compiler Backend

• Mescal uni-processor compiler back end
• Framework all in Xcode
• Input IR Xcode from front end (Lcode
  instruction set)
• Output machine dependent Xcode to Liberty
  simulator
• Machine description that we can reuse (from
  Lcode)
• HMDES, mainly for the scheduler
• Things to do
• Direct mapping code translator
• Code optimization
• Register allocation

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Machine Description

• Machine Description Framework

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Machine Description Part A

• Machine Code Description
• Code translation from Lcode instruction set to
  machine instruction set
• One-one mapping
• One-many mapping, e.g. compare and branch
• Intrinsic mapping, e.g. hard-to-generate
  instruction
• Code optimization within machine instruction set
• e.g. complex ALU instruction, post-increment load
• Code operand constraints
• 3 address or 2 address instruction or else
• Binding to special registers
• Illegal field (opposite to binding)

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Machine Description Part B, C

• HMDES (high level machine description language)
• Complete instruction list and reservation tables
• Resources, operations, latencies
• Compiler flags
• Miscellaneous ISA Information
• Special registers
• Memory alignment, endianness
• Function calling convention
• Branch delay slots, speculation/predication model
• Instruction sizes, etc.

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Conclusion

• Various views are needed
• Consistency issue
• Minimize redundancy
• Completeness of information
• Fast turn around time during architecture
  exploration
• Final product needs extra communication and
  programming
• Future goal
• A unified machine description covering the
  concurrent compiler, the uni-processor compiler,
  and the simulator