TGC Electronics Status

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TGC Electronics Status

• Osamu Sasaki 23 Dec. 2004 ???
• SLB ASIC
• PS-Board
• H-pT Board
• Star Switch
• Sector Logic
• Other boards
• Procurement
• 2004 ??

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TGC Electronics
DCS-PS
CPU
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SLB ASIC (1)

• Bugs of Version 4 (May 04) ? ?????
• Timing violation at memory WRITE cycle (from L1
  Buffer to De-randomizer Buffer)
• Any error does not appear when De-rand. Buffer is
  empty (no read-out queue).
• Between Address and WEB 0.3ns timing violation
  is shown by the simulation, which is taking into
  account the wire length and the load after the
  layout.
• Overflow counter of De-rand. Buffer does not
  work.
• The start number of L1ID shall be 0, not 1.
• Version 4-ECO (Oct. 04) ? ??
• Modification at gate layout level on CAD
• Additional delay (10 buffers) to clock signals
  for the address counter.
• Improved, however the error couldnt be fixed
  perfectly.
• The additional delay (1.2 ns) is NOT enough.
• Large input capacitance of WEB 0.25pF
• Skip a F/F for Overflow counter
• The Overflow counter does work properly.
• The bug of L1ID was not touched.

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SLB ASIC (2)

• Version 5 (Nov. 04) ? ??
• Modification from HDL level and improvement of
  timing margin
• The bugs of Version 4 were fixed.
• However, DOES NOT work at 40 MHz, up to 30 MHz.
• Serial-to-Parallel converters of read-out part
  (four 220-shift-registers) limit the speed.
• A CLK signal from a buffer with lowest driving
  power drives 440 D-F/Fs of the S-P converters.
• Obsolete design compiler (2000 Synopsys) was
  used, with un-proper options.
• Careless check after the layout !

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SLB ASIC (3)

• Version 4-ECO2
• Further modification of Version 4-ECO
• Modification at gate layout level on CAD
• Additional delay (20 buffers 2.4ns) to clock
  signals for the address counter.
• Buffers in front of each WEB input port of the
  memory
• Margin of the timing between ADDRESS and WEB is
  2.5 ns.
• Simulation using the back-annotated Standard
  Delay Format (SDF) file
• Except for memory write cycle (modification at
  gate layout level).
• Read-out works at up to 70 MHz and Trigger Matrix
  up to 54 MHz.
• Submitted 29/Nov. and chips in Feb. 05

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SLB ASIC Version 4-ECO2(delay and buffer)
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SLB ASIC (4)

• Version 6
• Modification of Version 5 from HDL level
• Design compiler (Rev. 2001 Synopsys) with proper
  option setting
• Each WEB port of the memories is driven by an
  individual buffer (BUF6).
• The numbers of fanouts for all signals are
  checked to be within reasonable numbers.
• Full simulation using the back-annotated Standard
  Delay Format (SDF) file.
• Except for INPUT BLOCK
• Margin of data write cycle in memories is larger
  than 1.8 ns.
• Read-out works at up to 69 MHz and Trigger Matrix
  up to 54 MHz.
• To be submitted in 2004. Chips in Feb.
• Mass-production takes two months. (April-May)
• Inspection takes one month.

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PS-Board

• 1344 PS-Boards and 100 Service Patch-Panel Boards
  are used for the system.
• 6 varieties of PS-Boards for TRIPLET PS-Pack
• PCBs of EWT0 will come in Dec.. Schematics of
  EWT1 finished.
• FT1, EWT2, EST and FT0 by end of March
• 10 varieties of PS-Boards for DOUBLETS PS-Pack
• Design by end of July
• 1 varieties for PS-Boards for EI/FI TGCs.
• 9U, 160mm VME-like board in HSC crate.
• Universal PS-Boards were developed for Test Beam
  and Test Assembly. 24 PS-Boards are available.
• PS daughter boards were mass-produced.
• Mass-production for Triplet
• Test of prototype boards by end of May.
• PCBs in April-June.
• Assembly in May-July.
• Inspection in June-Aug.

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H-pT Board and Star Switch Board

• H-pT Board (192 boards)
• 3 varieties of boards (endcap wire, endcap strip
  and forward)
• H-pT ASICs have been mass-produced.
• Forward H-pT Board was used at Test Beam.
• Minor modification will be done.
• Designs for Endcap by end of March
• SSW Board (lt 200 boards)
• All Anti-fuse FPGAs
• Irradiation tests of the parts have completed.
• SSW are being debugged at KEK.
• The SSW is working at up to 48 MHz. Comprehensive
  test will follow.

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Sector Logic and other boards

• 48 Sector Logic Boards for Endcap and 24 Sector
  Logic Boards for Forward
• Design of the final version has started.
• 100 Service Patch-Panel Boards
• To be ordered in Jan.
• Trigger module for commissioning
• Substitute for H-pT and SL
• Cosmic-ray trigger for 1/12
• Schematics finished this week.
• Inspection boards for H-pT ASIC and SLB ASIC
• Boards were assembled and being debugged.

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Procurement

• Parts of ladders for PS-Packs FIN.
• Except for long bars for Doublets
• Cases for PS-Boards and Service Patch-Panel
• Ordered. All parts of cases come in March. To be
  Assembled with PS-Boards and DCS Boards at CERN.
• CAT6 cables for PS-Boards to H-pT/SSW
• Labeled at both ends
• Tendering on 22 Dec.
• LV cables for Triplet
• Cables from LV Distributor Boxes to PS-Boards
• Labeled at both ends
• To be ordered in Dec.
• LV Distributor Boxes
• To be ordered in Jan.
• Electronics parts
• Most of them were ordered and delivered.
• FPGAs for SLs and OE/EO Tendering on 22 Dec.

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2004

• ?????
• SLB ASICs
• ??????????????
• ?????
• Collaboration
• within Japan
• with/against Israel
• ????
• Wine
• ??(?)????????