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JosephsonCMOS Hybrid Amplifier for Highspeed SFQtoCMOS Conversion

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... of the parasitic inductance of the serpentine array, made by treating a column ... (serpentine) --- 54 ps (Add 20 ps for Part 1) 4K CMOS Characteristics ... – PowerPoint PPT presentation

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Title: JosephsonCMOS Hybrid Amplifier for Highspeed SFQtoCMOS Conversion


1
Josephson-CMOS Hybrid Amplifier for High-speed
SFQ-to-CMOS Conversion Q. Liu, T. Van Duzer, X.
Meng, S. R. Whiteley Department of EECS,
University of California, Berkeley, USA and N.
Yoshikawa, Department of Electrical and Computer
Engineering, Yokohama National University,
Hodogaya, Yokohama, Japan Workshop on
Superconductive Electronics, Oct 19-23, 2003,
Loon Mtn., New Hampshire
Calculation of parasitic capacitance and
inductance of the array of 400 junctions    The
parasitic capacitance C0 is affected by the
proximity of the ground plane to the array and
the effective permittivity of the substrate. By
increasing the spacing between the ground plane
and the array (array treated as a continuous
sheet of metal) C0 is decreased. When the 40 mV
signal is applied to the gate of M1, the current
through the 400-JJ array exceeds the critical
current. Vout then drops by about 1 V from Vdd
in a time determined by the charging of C0. The
inductance of the array and the neighbor
capacitance have some little effect but C0 is the
main factor.     We set the gap to 50 mm as a
compromise. The resulting C0 is about 100 fF
this is assumed to be distributed uniformly among
the junctions in the serpentine array. The
spiral array is connected with the load at the
center since those components of C0 require more
discharging than the ones at the Vdd end. The
capacitance to ground along the array is taken to
vary linearly.
  • Conclusions
  • Experiments and simulations indicate that delays
    in the interface amplifier can be 100 ps or
    less.
  • The CMOS amplifier in an advanced process may be
    fast enough, and more convenient, for the
    interface.
  • Total access time for the hybrid memory is
    expected less than 750ps, which is a
    subnanosecond region.
  • Future work
  • High-speed testing of amplifier with Josephson
    junction load array (Part 2 and Parts 1 and 2)
  • Optimize the CMOS memory to get minimized access
    time.
  • Cross talk problem in CMOS memory core.
  • Testing with single-flux-quantum drivers
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