Extension of Asynchronous Design Automation Tools

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Extension of Asynchronous Design Automation Tools

• Michael Boyer
• Advisor Cherrice Traver
• Steinmetz Symposium 2005

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Introduction

• Synchronous (clocked)
• Clock skew
• Asynchronous (self-timed)

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Advantages of Asynchronous

• No clock skew problem
• Increased power efficiency
• Increased performance
• Greater tolerance of variation in operating
  conditions
• Greater frequency distribution of electromagnetic
  noise
• Component modularity

4
Real-World Examples

• Amulet 1, 2e, 3, 3i
• Oticon DigiFocus hearing aid
• Philips 80C51 microcontroller
• Intel RAPPID Project

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Phased Logic (PL)

• Automated translation
• Two phase LEDR signaling

E
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Liveness and Safety

• PL synthesis algorithm
• Guarantees liveness and safety
• Token abstraction

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Coarse-Grained PL

• Wrap logic blocks with PL circuitry
• Logic blocks
• Barrier blocks
• Through blocks
• Speed-up techniques
• Time borrowing
• Early evaluation

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Wrapper Circuit
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VHDL Modeling

• New models
• Wrapper models
• Environment models
• Assumptions
• Testing

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ATACS

• Automatic Timed Asynchronous Circuit Synthesis
  (ATACS)
• Automated verification
• Hazard checking

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Verification Example
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Results

• Wrapper for Through Blocks with Time Borrowing
• min(D1, D2, D3, D4) min(D5) max(C1)
  max(xorG) max(D-latch) min(C2) min(xorC)
  min(DFF)
• min(D1, D2, D3, D4) min(D5) max(compute)
  max(D-latch) min(C2) min(xorC) min(DFF)
• Wrapper for Through Blocks without Time
  Borrowing
• min(D1, D2, D3, D4) max(compute) max(D-latch)
  min(nC2) min(DFF) min(nC1)
• Wrapper for Barrier Blocks without Early
  Evaluation
• min(D1, D2, D3, D4) max(compute) max(Data DFF
  setup time) min(nC)

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Future Work

• Include results in mapping tool
• Use mapping tool to compare PL to synchronous
• Implement PL in hardware

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Acknowledgements

• Cherrice Traver, Union College
• Chris Myers, University of Utah
• Bob Reese, Mississippi State University
• IBM/SRC

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Questions?