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Extension of Asynchronous Design Automation Tools

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Synchronous (clocked) Clock skew. Asynchronous (self-timed) Advantages of Asynchronous. No clock skew problem. Increased power efficiency. Increased performance ... – PowerPoint PPT presentation

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Title: Extension of Asynchronous Design Automation Tools


1
Extension of Asynchronous Design Automation Tools
  • Michael Boyer
  • Advisor Cherrice Traver
  • Steinmetz Symposium 2005

2
Introduction
  • Synchronous (clocked)
  • Clock skew
  • Asynchronous (self-timed)

3
Advantages of Asynchronous
  • No clock skew problem
  • Increased power efficiency
  • Increased performance
  • Greater tolerance of variation in operating
    conditions
  • Greater frequency distribution of electromagnetic
    noise
  • Component modularity

4
Real-World Examples
  • Amulet 1, 2e, 3, 3i
  • Oticon DigiFocus hearing aid
  • Philips 80C51 microcontroller
  • Intel RAPPID Project

5
Phased Logic (PL)
  • Automated translation
  • Two phase LEDR signaling

E
6
Liveness and Safety
  • PL synthesis algorithm
  • Guarantees liveness and safety
  • Token abstraction

7
Coarse-Grained PL
  • Wrap logic blocks with PL circuitry
  • Logic blocks
  • Barrier blocks
  • Through blocks
  • Speed-up techniques
  • Time borrowing
  • Early evaluation

8
Wrapper Circuit
9
VHDL Modeling
  • New models
  • Wrapper models
  • Environment models
  • Assumptions
  • Testing

10
ATACS
  • Automatic Timed Asynchronous Circuit Synthesis
    (ATACS)
  • Automated verification
  • Hazard checking

11
Verification Example
12
Results
  • Wrapper for Through Blocks with Time Borrowing
  • min(D1, D2, D3, D4) min(D5) max(C1)
    max(xorG) max(D-latch) min(C2) min(xorC)
    min(DFF)
  • min(D1, D2, D3, D4) min(D5) max(compute)
    max(D-latch) min(C2) min(xorC) min(DFF)
  • Wrapper for Through Blocks without Time
    Borrowing
  • min(D1, D2, D3, D4) max(compute) max(D-latch)
    min(nC2) min(DFF) min(nC1)
  • Wrapper for Barrier Blocks without Early
    Evaluation
  • min(D1, D2, D3, D4) max(compute) max(Data DFF
    setup time) min(nC)

13
Future Work
  • Include results in mapping tool
  • Use mapping tool to compare PL to synchronous
  • Implement PL in hardware

14
Acknowledgements
  • Cherrice Traver, Union College
  • Chris Myers, University of Utah
  • Bob Reese, Mississippi State University
  • IBM/SRC

15
Questions?
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