Experiments with the Peripheral Virtual Component Interface

1
Experiments with the Peripheral Virtual Component
Interface

• Roman L. Lysecky, Frank Vahid, Tony D. Givargis
• Dept. of Computer Science Engineering
• University of California, Riverside
• also with the Center for Embedded Computer
  Systems, UC Irvine

This work was supported by the National Science
Foundation under grant CCR-9811164 , and by a
Design Automation Conference graduate scholarship.
2
Introduction

• Advent of Systems-on-a-Chip (SOCs) and cores

• Peripheral cores
• Microprocessor support components
• UARTs, DMA controllers, CODECs, off-chip bus
  interfaces, etc.

• Problem how integrate cores into different SOCs
  having different on-chip peripheral buses?

3
Introduction The Core Integration Problem

• Solution 1 User modifies core for specific bus
• Could accidentally change the cores functionality

• Solution 2 Different core version per bus
• Cant consider all buses

• Solution 3 Standard bus
• Not likely VSIA

• Solution 4 Bus wrappers
• Promising -- but how much overhead?

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Introduction

• Bus wrapper approach
• Proposed by Virtual Socket Interface Alliance
• Separate core into internals and bus wrapper

• PVCI Peripheral Virtual Component Interface --
  standard between wrapper and internals
• Eases integration
• Only bus wrapper need be modified for different
  buses

• What overhead comes with a bus-wrapper solution?

5
Setup for evaluating PVCI overhead

• Digital camera example
• Synthesizable RTL VHDL
• Synopsys synthesis, simulation and power analysis
• About 100,000 cells
• 3 versions of the CCD and CODEC peripherals
• Integrated
• Non-PVCI wrapper (bi-direct.)
• Designed before PVCI
• PVCI wrapper (uni-direct.)
• 2 peripheral buses
• ISA
• Custom

Digital camera
MIPS
MEM.
BIOS
System bus
BRIDGE
On-chip peripheral bus
CODEC
CCD
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PVCI general structure
On-chip peripheral bus
Bus wrapper

• Two uni-directional buses
• Handshake control
• Synchronous

wdata
rdata
val
ack
clock
read
address
PVCI
Peripheral core internals
Peripheral core
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Experiments with the ISA bus
Bus Master

• 23-bit address bus
• 32-bit bi-directional data bus
• 4-cycles per access minimum
• Slower peripherals can extend access time using
  iochrdy signal

isa_iochrdy
isa_addr
ack_data
isa_data
isa_ior
isa_iowi
isa_ale
Peripheral (Bus Slave)
clock isa_addr isa_ale isa_data isa_ior isa_iow is
a_iochrdy
data ready
start transfer
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Experiments with the ISA bus
PVCI vs. Integrated

• Size overhead of about 1000 gates per peripheral

• Power overhead of about 0.05 milliwatts (lt1)

• No performance overhead
• Since ISA has 4-cycle minimum access delay

9
Experiments with a custom peripheral bus
clock bus_addr bus_data bus_ior bus_rdy

• Similar to ISA, but...
• No 4-cycle minimum
• Handshake

• Performance overhead on reads can occur

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Experiments with a custom peripheral bus
PVCI vs. Integrated

• Size overhead of about 1000 gates per peripheral

• Power overhead of about 0.05 milliwatts (lt1)

• Performance overhead of about 5 in this example

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Experiments

• 1000 gates per core overhead is fairly small
• Typical peripheral core may have from 5000-20000
  gates Inventra library
• 0.05 milliwatts per core overhead is also small
• No performance overhead with ISA bus
• Performance overhead of 5 on reads with faster
  bus
• Essentially due to reads taking 4 cycles instead
  of 2 cycles

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Conclusions

• Overheads in size, power and performance of PVCI
  vs. Integrated core were small
• Only significant overhead was performance in
  certain case
• Our earlier work on pre-fetching can reduce or
  eliminate this overhead ISSS99, DATE00
• Remerging the bus wrapper with core internals can
  also reduce this overhead
• PVCI and non-PVCI cores were competitive
• Integration advantages of bus-wrapper approach
  seem to come with acceptable overhead