Memory Circuits

1
Lesson 5

• Memory Circuits
• Electrical Breakdown

2
Memory
3
EEPROM Layout
4
Trans Cross section
Psub
Ptype
5
Comparison

• Density / Si Real estate.
• Read/Write capability, cycles .
• Non Volatile Retention.
• Access time Random.

6
High Voltages High Electrical Fields gt
Breakdown

• Destructive Device structure rupture
  Insulator, package, metal melt..gtIrreversible
  damage.
• Non Destructive Breakdown of barrier to current
  flow within the junction.

7
Breakdown Mechanisms

• Junction Breakdown a) Avalanche, by Impact
  ionization. b) Zener BD, by E force on covalently
  bound electron to free the.
• Latch-Up regenerative bipolar-transistor action
  causes a clamped, low resistance path between VCC
  and Gnd.
• Hot Carriers Injection into the Oxide
  (fA-pA)gtModify FET Characteristic.
• Avalanche Pair Production Hot Carrier-gtAvalanche-
  gtHole injection-gtSubstrate( near drain) in
  Forward Bias to Source-gtElectron injection from
  Source-gt More Avalanche.
• Punch through Depletion regions for Source and
  Drain interact to reduce the Barrier for electron
  flow.
• Oxide BreakdownBreakdown strength of SiO2
  insulator6107 V/cm