Automatic Verification of Timing Constraints

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Automatic Verification of Timing Constraints

• Student Mohanad Shini . Advisor Mr. Itai
  Yarom .
• March 30, 2006

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Outline

• Introduction .
• What is Multi-Cycle Path .
• What is False Path .
• Description of the problem .
• Solution .
• Our project .
• Conclusion .

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Outline

• Introduction .
• What is Multi-Cycle Path .
• What is False Path .
• Description of the problem .
• Solution .
• Our project .
• Conclusion .

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Introduction

• Today devices are challenging million
  transistors multiple gigahertz.
• Unfortunately, the size and complexity of design
  constraints to build these designs are increasing
  exponentially.
• One quarter of design projects undergo more than
  10 iterations due to constraint issues .
• Traditional design methods have largely ignored
  the design-constraint problem.

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Introduction

• False paths and multi-cycle-paths (MCP) are
  timing exceptions that present a particularly
  difficult problem when trying to achieve timing
  closure in modern, high-performance designs.
• Typically, these exceptions, as well as all
  timing constraints, are considered late in the
  design cycle and are specified in response to
  timing problems during verification. For optimum
  timing results, all timing exceptions must be
  guaranteed to be correct.

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Outline

• Introduction .
• What is Multi-Cycle Path .
• What is False Path .
• Description of the problem .
• Solution .
• Our project .
• Conclusion .

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What is Multi-Cycle Path

• A multi-cycle path in a design is a
  register-to-register path through some
  combinational logic where if the source-register
  changes, the path will require N cycles (where N
  gt 1) before the computation is propagated to the
  destination register. In other words, if the
  source register changes, then the destination
  register should not change in the next N cycles
  under any delay condition .

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Example (MCP)
The circuit above takes the signals a_in and
b_in and inputs them to both an adder and
multiplier. A finite-state machine controls the
outputs such that the addition is driven out in
one clock cycle, while the multiplication is
driven out a cycle later. In other words, it
takes two cycles to produce the multiplication
result.
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Outline

• Introduction .
• What is Multi-Cycle Path .
• What is False Path .
• Description of the problem .
• Solution .
• Our project .
• Conclusion .

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What is False Path

• - A false path is a path through a circuit that
  cannot be responsible for the circuit delay and
  no sequence of vectors result in the propagation
  of an event along the path.
• - There are two types of false paths
  synchronous and asynchronous. Synchronous false
  paths are correct when the logic path cannot
  execute. Asynchronous false paths are correct if
  the source and the target flops of the paths are
  from asynchronous clock domains. Furthermore, a
  valid synchronization scheme is required.

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Example (Synchronous FP)

• Notice the register muxReg that controls the
  two muxes in the design is one-hot, and as result
  there is no path from the input in1 to the output
  out2. Therefore this path may be ignored when
  performing timing analysis.

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Example (Asynchronous FP) (CDC paths)
D
DA
DB
CLK A
CLK B

CDC Clock Domain Crossing
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Clock Domain Crossing Paths
D
DA
DB
CLK A
CLK B
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Clock Domain Crossing Paths

• Metastability

D
DA
DB
CLK A
CLK B
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Synchronizers
Circuits that conditions CDC signals in order to
reduce the probability of metastability
DA
CLK B
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CDC Synchronization

• Synchronizers
• Flip-flops in sequence reduce probability of
  metastability
• 2 D flip-flops is the most commonly used scheme
• But leads to unpredictable delay in signal
  propagation

data_in
data_out
sync
clk_a
clk_b
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Types Of Synchronizers

• Basic synchronizer (level signal) .
• Edge-detecting synchronizer .
• Pulse synchronizer .

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Types Of Synchronizers
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SDC Synopsys Design Constraints

• SDC file describes the design intent and
  surrounding constraints for synthesis, clocking,
  time, power, test and environmental and operating
  conditions.

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Outline

• Introduction .
• What is Multi-Cycle Path .
• What is False Path .
• Description of the problem .
• Solution .
• Our project .
• Conclusion .

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Description of the problem

• Textual mistakes .
• Missing time-to-market requirement .
• No method exists fo ensuring valid and consistent
  constraint formats in SDCs .
• difficult verification .
• Critical Impact .

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Description of the problem

• Textual mistakes
• Since the SDC files are entered in text
  format, it is possible for the designer to make
  mistakes that causes the constraints to be
  inconsistent with the design. For example, the
  SDC files might reference a signal name that is
  not actually in the design.
• Missing time-to-market requirement
• It is essential to eliminate fundamental
  problems as early in the design cycle as
  possible. If a designer applies flawed
  constraints to a design, he may be unable to
  mitigate problems that surface later without
  making sweeping changes to the design, which
  results in the projects missing its
  time-to-market goals.

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Description of the problem

• No method exists for ensuring valid and
  consistent constraint formats in SDCs.
• difficult verification
• The false-path and multi-cycle path
  exceptions that SDCs specify are difficult to
  verify in the design context.

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Description of the problem

• Critical Impact
• Incorrect timing constraints can leave chips
  with critical timing bugs that can cause recalls,
  re-spins, and redesigns, costing hundreds of
  thousands of dollars. Worse still, delays in
  getting to market and missed opportunities can be
  devastating.

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Outline

• Introduction .
• What is Multi-Cycle Path .
• What is False Path .
• Description of the problem .
• Solution .
• Our project .
• Conclusion .

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Automatic Verification of Timing Constraints

• Fortunately, Formal Verification can be used to
  analyze false path and multi-cycle path
  constraints and verify their correctness.
• SolidTC, a timing constraint verifier from
  Averant, applies formal verification technology
  to the problem of verifying timing constraints in
  complex, multi-million gate designs.

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Flow Through The Tool
Its important to note this is a RTL too. When a
path is reported as false, it is false under all
delay assignments to gates and wires.
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Outline

• Introduction .
• What is Multi-Cycle Path .
• What is False Path .
• Description of the problem .
• Solution .
• Our project .
• Conclusion .

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Goals of the project
The goal of this project is to provide a
verification flow for design constraints .

• Generate PSL (property specification language)
  checkers .

• Generating CDC (Clock Domain Crossing)
• Inputs (PI/PO, Clocks, Paths).

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Goals of the project

• Generate PSL checkers .

SDC
False and multicycle paths
PI/PO
Clocks
We want to ensure that these paths are really
false paths .
PSL Checkers
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Goals of the project

• CDC flow

Design
PI/PO
Clocks
CDC
Synchronous checkers
violations
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Flow of the project
Design
SDC
Violations
Constraints Verification
Checkers
Clocks
Formal Verification
CDC
Simulation
Violations
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Outline

• Introduction .
• What is Multi-Cycle Path .
• What is False Path .
• Description of the problem .
• Solution .
• Our project .
• Conclusion .

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Conclusion

• Achieving timing closure is a critical factor in
  producing reliable, bug-free, high-performance
  designs. The key to this is thorough design
  verification, being sure not to inadvertently
  relax the design tests through the application of
  incorrect timing constraints.

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Thanks For Listening