System on Programmable Chip

1
System on Programmable Chip (SoPC) for Real-Time
Control Applications
Dario L. Sancho-Pradel
(D.Sancho-Pradel_at_lboro.ac.uk)
Electronic Electrical Engineering Loughborough
University UK
2

• Background Problem Overview
• Proposed SoPC Architecture
• Implementation Methodology
• Practical Case
• Future Work

3
Background Control Basics
Physical System
Mathematical Model
Simplified model (Linearisation, )
Real-Time Equations
Transfer Function
State-Space (Continuous)

• Fast Control Loop Execution
• High Sampling Rates

(Discrete-Time)
4
Background Traditional Approach
Visual Environment
Design Simplicity
C/C
Other
Performance
Assembler

• DSP
• Micro-controller
• Microprocessor

External Logic
5
Background Traditional Problems
1. Off-the-shelf components
General devices ? Lower performances
2. Field of expertise
Control, Hardware, Software ? How to master all?
Application Specific Hardware FPGA EDA
High-Performance, Re-configurable, Automated
Programming
6
SoPC Architecture Overview
Remote Monitoring
SYSTEM TO BE CONTROLLED
Sensors IN
Op. Amp.
Ethernet
FPGA
mP
Embedded Controller
PWM Filter
Actuators OUT
In-situ
Wireless
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SoPC Architecture Description
FLASH
Analog In
EBI
RTC-SOPC
MM
SIM
mP
AHB
CSP II
Ethernet
Actions
FILTER
PORT
Control Kernel
SIM
External Interface
Plant
C
Output
Input

-
K
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SoPC Architecture Microprocessor

• Controller Programming
• Controller Commanding
• Background Coefficient Calculation
• (ADAPTATION)
• System Monitoring
• External Event Managing

FLASH
EBI
RTC-SOPC
MM
SIM
mP
AHB
CSP II
Ethernet
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SoPC Architecture CSP II
Adapting at e.g.10Hz
Sampling at e.g. 10kHz

• Very Fast Control Laws Execution
• Modified d approach
• Real Time Adaptation
• Re-programming
• AMBA (AHB) Bus Interface
• Seamless SoPC integration
• SAC (A/D) PWM (D/A) Units Integrated
• 1 Cycle MAC Instructions

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SoPC Architecture CSP II - Architecture
Error
Status
External
SAC
SAC
Interlocking
CFF-RAM (11 bits) (Buffer)
STV-RAM (27 bits) (Buffer)
Instruction Handler
Instruction Handler
CFF-RAM (11 bits)
STV-RAM (27 bits)
CL-RAM (Control Law)
CL-RAM (Control Law)
27
ADAPTATION
ADAPTATION
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PROGRAMMING
A
B
C
REPROGRAMMING
MAC (AB)
COMMANDS
PIPELINE
MAC (C)
D
AHB DECODER
AMBA (AHB) SLAVE INTERFACE
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SoPC Architecture CSP II (ISA)

• 32-bits RISC format
• Variables by REFERENCE
• Same Size Operands
• Single Execution Cycle
• 1 unused bit ?I.S. Expansion

Instruction dependency solved
Prospective Parallel Architectures
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SoPC Architecture Communication
CSP II INTERFACE SECTION
AHB Bus
mP Master Interface
D 2..0
enProg
AHB Slave Interface
Address Decoding Data Access
Interlocking
STATUS
CFF-RAM
D 10..0
D 20..0
D 31..0
A 9..2
A 9..2
mP
HSEL_CFF
HSEL_CFF
DECODER
A 13..10
A 13..2
HSEL_CL
ahb2slave _waddr
ack
A 31..0
HSEL_IL
HSEL_STV
SYNC.
CTL
D 20..0
CL RAM
A 9..2
ack
enProg
ahb2slave_we
A 9..2
ahb2slave _raddr
STV RAM
ahb2slave _re
slave2ahb_data
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Implementation Figures (Standard)
Device Family ARM-Based Excalibur Device Code
EPXA4 Logic Elements 16,640 (9) ESB
104 (lt12) ESB bits 212,992 (10) Typical
Gates 400,000
ESB Embedded System Blocks
Outputs 4 Inputs 16 Coefficients
128 State Variables 128 Instructions 256
UPGRADABLE
 
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Implementation Results
Actual Hardware
Theoretical
Quantisation
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Methodology Simulation
REAL SYSTEM
SYSTEM
Math Model
Control Law
Control Equations
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Methodology Compiler
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Practical Case HD Head Controller
1. Physical System
2. Mathematical Model (Reasonably Simplified)
W
J
3. Transfer Function
R
IACONST
4. State-Space
V
L
i
Estator
Armature
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Practical Case HD Head Controller
4. Controller Design
q(s)
qR(s)
E(s)
V(s)
---gtPRAGMAlt---- IN 1,u
---gt Y lt----
MUL y,c1,x1 MAC y,c2,x2,y
MAC y,d,u,y
---gt X1 lt---- MAC
x1,a1,x2,x1 ---gt X2tmplt----
MAC x2tmp,a2n,x1,x2
MAC x2tmp,a2n,x2,x2tmp ---gt X2 lt----
MAC x2,b2,u,x2tmp ---gt OUTPUT
lt---- WRITE 0,1,x1,x2
---gt Y lt---- 001-0000001-0000000-0000010-0000000 0
00-0000001-0000001-0000011-0000001 000-0000001-000
0010-0000100-0000001 ---gt X1 lt---- 000-0000010-000
0011-0000011-0000010 ---gt X2tmplt---- 000-0000101-0
000100-0000010-0000011 000-0000101-0000100-0000011
-0000101 ---gt X2 lt---- 000-0000011-0000101-0000100
-0000101 ---gt OUTPUT lt---- 011-0000000-0000001-000
0010-0000011
1kHz
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Future Work Maglev Train
Transrapid International Transrapid Test Facility
in Emsland, Germany
Tokyo - Osaka Japan
Baltimore-Washington U.S.A.

• Projects Goals
• Suspension/Levitation control
• Single-Chip solution
• Real-Time performances
• Easy to programme/re-programme

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System on Programmable Chip (SoPC) for Real-Time
Control Applications
Dario L. Sancho-Pradel
(D.Sancho-Pradel_at_lboro.ac.uk)
Electronic Electrical Engineering Loughborough
University UK