Design Excitement: An 8bit 200 MHz DAC

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Design ExcitementAn 8-bit 200 MHz DAC

• Sam Blackman
• Professor Bob Brodersen
• November 16, 1999

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Goal from Capn Vanderhaegen

• Specifications for DAC determined by SNR
  requirements at the receiver. Magic 30 dB
• Design tradeoffs speed/resolution of DAC vs.
  filter requirement.
• In digital domain, pulse shaping filter
  complexity increases with DAC speed. Since
  digital, can just add more taps.
• In analog domain, smoothing filter requirements
  decrease with DAC speed. At 200 MHz, only need a
  simple one pole RC filter.
• System level simulations were performed in MATLAB
  to verify functionality.

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Topology Possibilites 1

• Resistor ladder
• Simple good!
• Poor matching due to low CMOS resistor tolerances
  rules it out

• Charge division
• Again, relatively simple
• Low CMOS capacitance tolerances rule it out
• 2N caps large area!

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Topology Possibilities 2

• Current Division
• Stack of transistors above IREF reduces output
  voltage range (Razavi)
• Need huge IREF transistor
• No one uses it!

• Current Steering
• Excellent INL/DNL performance (with thermometer
  coded input)
• Can segment design to save area
• Matching can be controlled to any degree necessary

5
So How Much To Segment?
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Topology Decision

• 100 Segmented, baby.
• Binary-weighting has many disadvantages
  (non-monotonicity, poor linearity) and only one
  advantage area savings
• For 8-bit accuracy specification, this is not a
  factor especially on gigantic pin-limited
  testchip.
• Limited design time due to unexpected shift in
  research emphasis ?

• So now what?
• Key block is the current source cell
• Minimize area since there are 2N!
• How small can transistors be?
• How much current should be sourced?

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Current Source Design

• Current Sources
• Design considerations have four main factors,
  need to optimize
• Power
• Matching
• SNR
• Speed

Ian asks Why PMOS based? Cross talk reduction
from digital portions of the chipPMOS devices
built in n-well and thus shielded from the
substrate.

• Power is easy
• Simply number of current sources power dissipated
  per source

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Noise

• Noise
• Top device is main noise source can ignore
  cascoded transistor.
• Noise power doubled to account for biasing device
  and current cell frequency at 30 MHz to account
  for worst case (only 12.5 MHz baseband!)
• Good to have some margin due to additive coherent
  noise from bias, also flicker noise may be
  contributing
• Simulation matched calculated values extremely
  well for one current source. When the entire
  design was simulated, however, SNR dropped
  substantially. Luckily designed with plenty of
  margin!

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Matching

• Pelgrom 1989 baby
• Each current source controlled by bits of digital
  input word, and must have an error lt ½ LSB. No
  problem for LSB, but for MSB stringent
  requirement
• MSB built by wiring up 2N-1 current sources in
  parallel, and can then approx. INL by adding
  variances. Need INL to be less than ½.
• Now need to solve for acceptable standard
  deviation for unit current source. Can get rough
  estimation by solving p(INLlt1/2 LSB), but Bastos
  performed a Monte Carlo simulation to calculate
  more accurate figure. This corresponds to a yield
  of 99.
• Finally can solve for (WL)min using Pelgroms
  formula -- A?, AVT, VGS, and VT are process
  parameters, I is the current generated by a given
  source and ?I is the relative standard deviation
  of one current source. So what does this tell us?
  For ST matching numbers, minimum WL 2 um2. No
  problem!

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Speed

• DAC has to run at 200 MHz.
• Simple speed estimation
• Driving cap filter of around 5 pF
• Max voltage swing around 2 volts.
• Thus
• This drove design decision of 10 uA of current
  per source, for a total of 2.56 mA current.
• Simulated fine with 10 pF of load cap.

The Vengabus is coming, and everybodys jumping